Semiconductor memory and method of manufacturing the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKazutami Arimoto
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKazutami Arimoto
Estimating the term…
A semiconductor memory comprises a p.sup.- -type semiconductor substrate (1), a p-type epitaxial layer (15) and p.sup.+ -type epitaxial layers (16, 17) formed thereon, an n.sup.+ -type region (6) formed on the p.sup.+ -type epitaxial layer (16) to serve as a bit line, an n.sup.+ -type region (5) formed on the p.sup.+ -type epitaxial layer (17) to serve as a charge storage region and a gate electrode (9) formed on the p-type epitaxial layer (15) to serve as a word line. The p.sup.+ -type epitaxial layers (16, 17) prevent passage of electrons within electron-hole pairs induced by alpha rays, to suppress occurrence of soft errors. The p-type epitaxial layer (15) defines a region corresponding to the channel region of a bus transistor, whereby the impurity concentration thereof can be easily controlled, to readily set the threshold voltage of the bus transistor at an appropriate level.
A semiconductor memory comprising:
Dependencies are inferred from the claim text.