Method of combining gate array and standard cell circuits on a common semiconductor chip

A method of making a logic chip which includes the steps of

• defining a plurality of contiguous cell locations, each having a boundary, within a semiconductor chip,
• forming first and second standard cell circuits in spaced apart first and second cell locations, respectively, of said plurality of cell locations, each of said standard cell circuits being disposed within an active area of its associated cell location spaced at least a given distance from the boundary of its associated cell location,
• forming a first gate array cell in a third cell location of said plurality of cell locations contiguous with said first cell location between said first and second cell locations, said first gate array cell having an active circuit area spaced at least a given distance from the common boundary between said first and third cell locations, and
• forming a second gate array cell in a fourth cell location of said plurality of cell locations contiguous to said second cell location between said first and second cell locations, said second gate array cell having an active circuit area spaced at least said given distance from the common boundary between said second and fourth cell locations.

A method of making a logic chip which includes the steps of

• defining a plurality of contiguous cell locations, each having a boundary, within a semiconductor chip,
• forming a first and second cell of a first type in spaced apart first and second cell locations, respectively, of said plurality of cell locations, each of said first and second cell locations having an active circuit area spaced a given distance from the boundary of its associated cell location,
• forming a first cell of a second type in a third cell location contiguous with said first cell location between said first and second cell locations, the first cell of said second type having an active circuit area spaced at least a given distance from the common boundary between said first and third cell locations and extending to at least the boundary of said third cell location on its opposite side, and
• forming a second cell of said second type in a fourth cell location of said plurality of cell locations between said first and second cell locations, said second cell of said second type having an active circuit area spaced at least said given distance from the common boundary between said second and fourth cell locations and extending to at least the boundary of said fourth cell location on its opposite side.