Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology

A method of forming an NPN bipolar transistor on a first region of P type material of a substrate, the method comprising:

• forming an N well in the first region of P type material of the substrate;
• forming at least one field oxide region on said substrate on said N well to separate a collector region from a base region of said NPN transistor;
• implanting P type material into a predetermined region of said N well, said predetermined region to serve as the base region of the NPN bipolar transistor;
• forming an implant resistant layer of polysilicon material on at least a portion of said predetermined region in which P type material has been implanted;
• etching an emitter hole through the layer of polysilicon material;
• implanting N type material to the device through the emitter hole to form an emitter region of the NPN transistor and simultaneously shielding from doping the remaining portion of said region underlying said polysilicon material from such implanting;
• implanting N type material into the collector region of the NPN transistor;
• and
• implanting P type material into the base region of the NPN transistor.

A method of forming a floating gate avalanche metal oxide semiconductor (FAMOS) structure, an NPN bipolar transistor, an N-channel field effect transistor (NMOS) and a P-channel field effect transistor (PMOS) on a body, said method comprising:

• forming, in the same process steps, N type material reservoirs on areas of P type material on said body, said reservoirs of N type material corresponding to sites for formation of the PMOS and NPN structures;
• forming, in the same process steps, regions of P type material on said body, at least one of said regions of P type material formed to serve as a threshold voltage adjust implant of the FAMOS structure, and at least one of said regions portion of said P type material formed on said N type material reservoir of said NPN transistor to serve as a base layer for the NPN transistor;
• forming a layer of oxide for gates of MOS transistors and for resisting passage of implants from superior layers in regions aligned over portions of said base layer of P type material of the NPN transistor;
• forming, in the same process steps, regions of a first polysilicon layer on said body, at least one of said regions of a first polysilicon layer aligned over a portion of said base layer of P type material of the NPN transistor and at least one portion of said regions of a first polysilicon layer being formed to align with said threshold voltage adjust implant region at the site of the FAMOS structure;
• forming, in the same process steps, an interlayer oxide layer on the regions of said first polysilicon layer;
• forming a second layer of polysilicon material over the body;
• etching, in the same process steps, an emitter hole through the first and second layers of polysilicon material, thereby exposing the site of the emitter of the NPN transistor, and etching through the first and second layers of polysilicon material of the FAMOS structure to form the stack gate structure of the FAMOS structure and also thereby exposing the sites of the source and drain of the FAMOS structure;
• implanting, in the same process steps, N type material into said sites of the source and drain of the FAMOS structure exposed through said first and second layers of polysilicon materials, and also implanting N type material into said site of said emitter of said NPN transistor exposed through said first and second layers of polysilicon material;
• forming a layer of photoresist on the body on said second layer of polysilicon material;
• patterning said first layer of photoresist to provide a protective region of photoresist over the emitter hole of the NPN transistor, over the source and drain and stack gate regions of the FAMOS, and over predetermined regions of the second layer of polysilicon material to serve as gates for the NMOS and PMOS structures;
• etching said second layer of polysilicon material to form gates for the NMOS and PMOS structures;
• implanting, in the same process steps, N type material into regions on the body to form a collector region of the NPN transistor and a source region and drain region of the NMOS structure;
• and
• implanting, in the same process steps, P type material in regions of the body to form a base region of the NPN transistor and a source region and drain region of the PMOS structure, whereby during said implanting of said P type material to form the base region of the NPN transistor, said region of first polysilicon material aligned over said base layer functions as a self-aligned implant mask.

A method of forming a floating gate structure for a floating gate avalanche metal oxide semiconductor (FAMOS) and an emitter structure for an NPN transistor on a body comprising:

• forming in the same process steps N type material reservoirs on areas of P type material on a body;
• forming in the same process steps regions of P type material on said body, at least one of said regions of P type material formed to serve as a threshold voltage adjust implant of the FAMOS structure, and at least one of said regions of P type material formed on said N type material reservoir of said NPN transistor to serve as a base layer for the NPN transistor;
• forming in the same process steps implant resistant regions of a first polysilicon containing layer on said body, at least one of said regions of a first polysilicon layer aligned over a portion of said base layer of P type material of the NPN transistor and at least one portion of said regions of a first polysilicon layer being formed to align with said threshold voltage adjust implant region at the site of the FAMOS structure;
• forming in the same process steps an interlayer oxide layer on the regions of said first polysilicon layer;
• forming a second polysilicon material over the body;
• etching in the same process steps an emitter hole through the first and second layers of polysilicon material, thereby exposing the site of the emitter of the NPN transistor, and etching through the first and second layers of polysilicon material of the FAMOS structure to form a stack structure of the FAMOS transistor and also thereby expose sites of source and drain of said FAMOS transistor;
• implanting in the same process steps N type material into said exposed sites of the source and drain of the FAMOS transistor and into said exposed emitter of the NPN transistor.