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US 4,752,819 AGranted
Semiconductor integrated circuit device having a carrier trapping trench arrangement
AssigneesHitachi, Ltd., Hitachi Microcomputer Eng.
InventorYoshihisa Koyama
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Abstract
Herein disclosed is a DRAM which has such a carrier trapping region around a memory cell array as can trap minority carriers deep in a semiconductor substrate so that the minority carriers to be generated in the semiconductor substrate by alpha rays may be sufficiently trapped. The memory cell of the DRAM has a capacitor which is partially formed of the semiconductor substrate. The carrier trapping region is formed by making use of trenches or a well region.
Claims24
A semiconductor integrated circuit device comprising:
- a semiconductor substrate of a first conductivity type having a first main surface;
- a memory cell array formed on said semiconductor substrate and including a plurality of memory cells arrayed in rows and columns, wherein each said memory cell comprises a MISFET and a capacitor connected in series with each other, wherein said capacitor is formed by using a first trench formed in the first main surface of said semiconductor substrate, said capacitor having a first insulating film formed on the surface of said first trench and a first electrode formed over said first insulating film;
- a peripheral circuit formed in said semiconductor substrate in portions other than said memory cell array;
- and
- a carrier trapping region formed in said semiconductor substrate between said memory cell array and said peripheral circuit, wherein said carrier trapping region comprises second trenches formed in the main surface of said semiconductor substrate, insulating films which are formed on the surface of said second trenches, and second electrodes made of a conductive material formed over the surface of said insulating films in said second trenches.
2 more elements
A semiconductor integrated circuit device comprising:
- a semiconductor substrate of a first conductivity type having a first main surface;
- a memory cell array formed on said semiconductor substrate and including a plurality of memory cells arrayed in rows and columns and a plurality of data and word lines, wherein each said memory cell comprises a MISFET and a capacitor connected in series with each other and each said memory cell is selected by choosing predetermined data and word lines, wherein said capacitor is formed by using a first trench formed in the first main surface of said semiconductor substrate, said capacitor having a first insulating film formed on the surface of said first trench and a first electrode formed over said first insulating film;
- a peripheral circuit formed in said semiconductor substrate in portions other than said memory cell array and said peripheral circuit is comprised of a plurality of MISFETs;
- and
- a carrier trapping region formed in said semiconductor substrate between a memory cell located at the end of each row or column in said memory cell array and said peripheral circuit, wherein said carrier trapping region comprises second trenches formed in the main surface of said semiconductor substrate, insulating films which are formed on the surface of said second trenches, and second electrodes made of a conductive material formed over the surface of said insulating films in said second trenches.
2 more elements
Dependencies are inferred from the claim text.