Duty cycle timer

An improved duty cycle timer for providing a duty cycle control signal, said duty cycle control signal having alternate "on" and "off" intervals of different logic states, said timer comprising:

• integrated circuit means including first clock signal generating means for generating a first frequency clock, second clock signal generating means for generating a second frequency clock independent of said first clock, first electronic counting means comprising a first multistage binary counter responsive to said first clock for measuring a predetermined one of said "on" and "off" time intervals and providing a signal representative of the completion thereof, and second electronic counting means comprising a second multistage binary counter responsive to said second clock for measuring the other one of said "on" and "off" time intervals and providing a signal representative of the completion thereof, said interval measured by said first electronic counting means being longer than said interval measured by said second electronic counting means and said signals representative of the completion of said "off" and said "on" time intervals being provided by the respective final operative stages of the respective said multistage counters;
• circuit means, including resetting circuitry, cross-connecting said first and said second electronic counting means in complementary relation for initiating said measurement of said "on" and said "off" time intervals respectively from a reset condition of the respective one of said first and said second electronic counting means in response to said signals representative of the completion of the preceding said "off" and "on" time intervals respectively, each said multistage counter being reset by the application of a particular logic signal level to a respective reset input to the respective said counter, said counter being maintained in said reset condition while said particular logic signal level is maintained at said reset input, and wherein said cross-coupling of said first and second electronic counting means coupler the respective said signals representative of completion of said "off" and said "on" intervals to the respective said reset inputs of the respective said counters to thereby at least release said reset condition;
• and
• wherein said duty cycle control signal is provided by at least one of said first and said second electronic counting means.

An improved defrost timer for providing a defrost timing control signal, said timing control signal having alternate "ON" and "OFF" intervals of different logic states, said timer comprising:

• means including first and second different RC time constants for generating respective first and second electronic clock signals at rates different from and independent of each other, said clock signal generating means being responsive to a two-state "enable or hold" control signal for respectively enabling or inhibiting generation of said first and second clock signals by said electronic clock signal generating means;
• electronic counting means responsive, in alternate succession, to the first clock for a first interval and to the second clock for a second interval to provide an output signal representative of an "OFF" interval during said first interval until a first predetermined count is reached and representative of an "ON" interval during said second interval until a second predetermined count is reached, said "ON" and said "OFF" time intervals respectively being initiated by the completion of the preceding "OFF" and "ON" time intervals respectively and said defrost timing control signal being provided by said output signal of said electronic counting means;
• and
• means for connecting a two-state "enable or hold" control signal to said clock signal generating means, so that said first and second clock signals are held frozen and any count in said electronic counting means remains static during application of said "hold" control signal to said clock signal generating means.