Circuit arrangement to generate squarewave signals with constant duty cycle

A circuit arrangement for providing at an output terminal a square wave signal having the same recurrence frequency as the recurrence frequency of an input signal and wherein said square wave signal exhibits a predetermined duty cycle, said circuit arrangement comprising:

• a flip-flop having set and reset states and having an output coupled to said output terminal for providing an output signal representative of said set and reset states, said set state being selected responsive to each recurrence of said input signal and said reset state being selected responsive to a reset signal;
• first controllable integrator circuit means having a control input coupled to said output terminal for providing a first ramp signal changing in first and second polarity directions during said set and reset states of said flip-flop, respectively;
• second controllable integrator circuit means having a control input coupled to said output terminal for providing a second ramp signal changing in said second and first polarity directions during said set and reset states of said flip-flop, respectively;
• a comparator having first and second inputs coupled to said first and second controllable integrator circuit means, respectively, and an output coupled to said flip-flop for providing thereto said reset signal responsive to said first and second ramp signals being substantially equal.