Method of manufacturing a semiconductor random access memory element
AssigneeOki Electric Industry Co., Ltd.
InventorsAkio Kita, Masayoshi Ino
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Abstract
The semiconductor memory element comprises two capacitors and a switching MOS transistor. A first capacitor is constituted by a silicon semiconductor substrate, a thin oxide film and a first doped polycrystalline silicon layer, and a second capacitor is constituted by a second doped polycrystalline silicon layer, a thin oxide film between the first and the second doped polycrystalline silicon layers, and the first polycrystalline silicon layer. Interconnection layers necessary to form a single transistor type dynamic memory cell are also provided.
Claims1
A method of manufacturing a semiconductor random access memory element including a storage region in the form of a stacked structure and an N-type MOS transistor region on a surface of a silicon semiconductor substrate, said method comprising the steps of:
- (a) preparing a silicon semiconductor substrate of a P conductivity type;
- (b) forming first and second field silicon oxide layers on a selected surface of said substrate and a channel stopping layer of a P conductivity type beneath said first and second oxide layers, said first and second oxide layers defining said storage region and said N-type MOS transistor region to be formed;
- (c) forming a first dielectric layer of silicon dioxide on a surface of said storage region;
- (d) depositing a polycrystalline silicon layer on the entire surface of said first dielectric layer by chemical vapor deposition;
- (e) diffusing phosphorous atoms at a high concentration into said polycrystalline silicon layer to convert it a conductive layer, while forming an N.sup.+ diffused region contiguous to said second field silicon oxide layer and in said N-type MOS transistor region;
- (f) selectively removing said conductive layer to form a common capacitor plate, one end of said common capacitor plate being electrically in contact with said N.sup.+ diffused region;
- (g) forming a second dielectric layer of silicon dioxide on a surface of said common capacitor plate;
- (h) forming a second conductive plate of doped polycrystalline silicon on the surface of said second dielectric layer, said second conductive layer being in contact with a substrate bias potential;
- (i) forming a third silicon dioxide layer on the entire surface of the structure obtained by the step (h);
- (j) then forming a third doped polycrystalline silicon layer on the surface of said third silicon dioxide layer;
- (k) patterning said third doped polycrystalline silicon layer and said third silicon dioxide layer to form a gate oxide layer and a gate electrode in said MOS transistor region;
- (l) forming a source region extending from said N.sup.+ region, said a drain region in said MOS transistor region;
- (m) applying an insulating layer of phosphorous silicate glass on the surface of the structure obtained by the step (l);
- (n) forming a contact aperture in said insulating layer so as to expose a surface of said drain region;
- and
- (o) forming a metal layer acting as a bit line on a surface of said insulating layer, said metal layer being in contact with said drain region.
Dependencies are inferred from the claim text.