Electrostatic discharge protection device for CMOS integrated circuit outputs
AssigneeAdvanced Micro Devices, Inc.
InventorsYow-Juang B. Liu, Salvatore Cagnina
Life of this patent
Estimating the term…
Abstract
An integrated circuit device for protecting the circuitry of an integrated circuit from an electrostatic discharge into an output pin of the chip is disclosed. In a preferred embodiment, the device comprises an n-well, n-channel, polysilicon-gated FET structure, which operates in a punch-through mode, coupled to an output pad and an output buffer of the circuit. Back biasing in the chip system affords additional inhibition to turn-on during normal system operation.
Claims12
An electrostatic protection device for a semiconductor substrate integrated circuit having at least two reference potential levels, an output pad, a first n-channel transistor having a drain terminal coupled to the more positive of said reference potential levels, a source terminal coupled to said output pad, and a gate terminal coupled to an output of said circuit, and a second n-channel transistor having a drain terminal coupled to said output pad, a source terminal coupled to the more negative of said reference potential levels, and a gate terminal coupled to an output of said circuit, characterized by:
- at least one n-channel transistor having a drain terminal coupled to said output pad, a source terminal coupled to said more negative of said reference potential levels, and a gate coupled to said output pad, the at least one transistor having a punch-through voltage higher than the highest voltage reached by said output pad during normal operation of said circuit and lower than the failure voltage of both the first and second transistors.
An ESD protection semiconductor device for a an integrated circuit having a reference potential Vss and an output pad connected to an output of the circuit, comprising:
- an n-well, n-channel FET having a source, a drain and a channel region and having a semiconductor gate isolated from the channel region by a relatively thick field dielectric layer, said gate and said drain coupled to said output pad and said source coupled to said Vss, such that said FET turns on at a voltage which forces said FET into a punch-through mode during an ESD occurrence into said pad,
- said integrated circuit also having a back bias voltage, wherein said punch-through mode occurs at approximately twice the voltage of a circuit not having said back bias.
An electrostatic discharge (ESD) protection device for an output of an integrated circuit, the integrated circuit having an output buffer connected to a connection pad, the device comprising an ESD field effect transistor having its drain and gate terminals connected to the connection pad and having its source terminal connected to a source circuit potential, the ESD transistor having dimensions and doping levels such that it turns on when an electrostatic discharge voltage on the connection pad reaches a first voltage level, the first voltage level being less in magnitude than the failure voltage of the output buffer, turn-on of the ESD transistor being in the punch-through mode.
An electrostatic discharge protection device for an output of an integrated circuit, the integrated circuit having an output buffer comprising first and second transistors, the first transistor having a gate terminal, a drain terminal coupled to a Vcc reference potential level and a source terminal coupled to an output pad, the second transistor having a gate terminal, a drain terminal coupled to the output pad and a source terminal coupled to a Vss reference potential level, the device comprising an ESD field effect transistor having its drain and gate terminals connected to the output pad and having its source terminal connected to a source circuit potential, the ESD transistor having dimensions and doping levels such that it turns on when an electrostatic discharge voltage on the output pad reaches a first voltage level, the first voltage level being much less than the gated diode breakdown voltage and the junction breakdown voltage of both the first and second transistors, but greater than the highest voltage reached by the output pad during normal operation of the integrated circuit, turn-on of the ESD transistor being in the punch-through mode, wherein the ESD transistor comprises:
- a p-type substrate;
- an n-type drain well region in the substrate;
- an n-type source well region in the substrate;
- a channel region in the substrate, separating the drain well region and the source well region;
- an insulator layer superposing the substrate, the gate terminal superposing the insulator layer over the channel region;
- a drain terminal region in the drain well region, the drain terminal region being doped n.sup.+, the drain terminal being coupled to the drain terminal region;
- and
- a source terminal region in the source well region, the source terminal region being doped n.sup.+, the source terminal being coupled to the source terminal region.
Dependencies are inferred from the claim text.