Process for manufacturing semiconductor memory device
AssigneeHitachi, Ltd.
InventorOsamu Tsuchiya
Life of this patent
Estimating the term…
Abstract
A dynamic RAM having a memory cell constituted by a capacitor element, utilizing a trench or moat formed in a semiconductor substrate, and a MISFET. One of the electrodes of the capacitor element is connected to the MISFET constituting part of the memory cell at the side wall of the upper end of the moat for forming the capacitor element. This electrode is connected in self alignment with a semiconductor region which serves as either the source or drain of the MISFET.
Claims22
A process for manufacturing a semiconductor integrated circuit device having a capacitor, with one electrode of the capacitor adapted to be electrically connected to a first semiconductor region formed in a semiconductor substrate, said process comprising the steps of:
- forming a first mask on the main surface of said semiconductor substrate;
- forming a relatively shallow moat in said semiconductor substrate by employing said first mask, said relatively shallow moat having a side wall and a bottom;
- forming a second mask on the side wall of said shallow moat, said second mask being formed of an oxidation impermeable film, the bottom of the relatively shallow moat being exposed through the second mask;
- forming a relatively deep moat, said deep moat being formed by etching the bottom of said shallow moat exposed through said first and second masks;
- forming an oxide film by thermal oxidation of the surface of said semiconductor substrate exposed in said deep moat by employing said second mask;
- removing said second mask, thereby exposing the surface of said semiconductor substrate at the upper end of the side wall of said deep moat;
- and
- forming said one electrode in said deep moat, said one electrode being adapted to be electrically connected to said first semiconductor region through a portion of said substrate exposed by removing said second mask.
A process for manufacturing a semiconductor integrated circuit device having a semiconductor element in a trench formed in a semiconductor substrate, with an electrically conducting member of the semiconductor element being adapted to be electrically connected to a semiconductor region formed in the semiconductor substrate, comprising the steps of:
- forming a relatively shallow moat in said semiconductor substrate, said relatively shallow moat having a side wall and a bottom;
- forming a mask on the side wall of said relatively shallow most, said mask being formed on an oxidation impermeable film, the bottom of the relatively shallow moat being exposed through the mask;
- forming a relatively deep moat, said deep moat being formed by etching the bottom of said relatively shallow moat;
- forming an oxide film by thermal oxidation of the surface of said semiconductor substrate exposed in said deep moat by employing said mask;
- removing said mask, thereby exposing the surface of said semiconductor substrate at the upper end of the side wall of said deep moat;
- and
- forming said electrically conducting member in said deep moat, said electrically conducting member being adapted to be electrically connected to said semiconductor region through the surface of the semiconductor exposed by removing said mask.
Dependencies are inferred from the claim text.