Semiconductor device with input and/or output protective circuit

A semiconductor device comprising a semiconductor substrate of one conductivity type, an input terminal supplied with an input signal, a well region of opposite conductivity type formed in said substrate, an insulated gate field effect transistor formed in said well region, a first region of said opposite conductivity type formed in said substrate and having a junction depth shallower than said well region, a first conductive layer connecting said input terminal to said first region, a second conductive layer connecting said first region to the gate of said transistor, a second region of said opposite conductivity type formed in said substrate and disposed between said first region and said well region, said second region having a junction depth substantially equal to the junction depth of said well region and completely surrounding said first region, and a third conductive layer supplying said second region with a bias potential that reversely biases a PN junction formed between said second region and said substrate.

A semiconductor device comprising a semiconductor substrate of one conductivity type, a well region of opposite conductivity type formed in said substrate, a first field effect transitor having source and drain regions of said one conductivity type formed in said well region, a second field effect transistor having source and drain regions of said opposite conductivity type formed in said substrate, a third field effect transistor having source and drain regions of said opposite conductivity type formed in said substrate separately from said second transistor, an input terminal, a polycrystalline semiconductor layer formed between said input terminal and one of said source and drain regions of said third transistor, a first conductor layer formed between said one of said source and drain regions of said third transistor and the gates of said first and second transistors, a semiconductor region of said opposite conductivity type formed in said substrate so as to surround said third transistor with a junction depth substantially equal to the junction depth of said well region, said semiconductor region completely surrounding said third transistor, and a second conductive layer supplying a bias potential to said semiconductor region to reverse-bias a PN junction formed between said semiconductor region and said substrate.

A semiconductor device comprising a semiconductor substrate of one conductivity type, a pad on an insulating film provided on said semiconductor substrate, a first region of an opposite conductivity type formed in said semiconductor substrate, a resistor layer of polycrystalline silicon on an insulating film provided on said substrate and electrically connected between said pad and said first region, an insulated gate field effect transistor formed in said semiconductor substrate and having a gate electrode electrically connected to said first region, and a second region of said oposite conductivity type formed in said semiconductor substrate and disposed between said first region and said insulated gate field effect transistor, said second region completely surrounding said first region in a plan view of the device.

A semiconductor device comprising a semiconductor substrate of one conductivity type, an input pad formed on an insulating film over said semiconductor substrate, a first region of an opposite conductivity type formed in said dsemiconductor substrate and electrically coupled to said input pad, a field effect transistor formed in said semiconductor substrate and having a gate electrically connected to said first region, a second region of said opposite conductivity type formed in said semiconductor substrate in parallel with said first region, a gate electrode formed on an insulating layer covering a portion of said semiconductor substrate betweeen said first and second regions, said first region, said second region and said gate electrode forming another field effect transistor, means for electrically connecting said gate electrode and said second region to a reference voltage, and a third region of said opposite conductivity type disposed beteen said first region and said field effect transistor and completely surrounding said another field effect transistor in a plan view of the device.