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US 4,731,696 AGranted
Three plate integrated circuit capacitor
AssigneeNational Semiconductor Corporation
InventorsPeter G. Himes, John A. Lippert
Life of this patent
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Abstract
A capacitor is described having a very low voltage coefficient of capacitance and a relatively large capacitance per unit area. A process is detailed for forming such a capacitor on an IC. The process is fully compatible with conventional IC processing and does not add substantially to the number of steps.
Claims7
A capacitor suitable for fabrication on a monolithic silicon integrated circuit, said capacitor having a low voltage coefficient and comprising:
- a first plate composed of a material selected from the group consisting of refractory metals and refractory metal silicides;
- a first dielectric layer located on said first plate, said first dielectric being characterized as having a low incidence of interface trapping states where it contacts the first plate;
- a second plate located on said first dielectric layer, said second plate composed of a material selected from the group consisting of refractory metals and refractory metal silicides;
- a second dielectric layer located on said second plate, said second dielectric being characterized as having a low incidence of interface trapping states where it contacts the second plate;
- a third plate composed of a conductive metal and located over said second dielectric layer;
- and
- means for connecting said first and third plates together to form one capacitor electrode wherein said second plate forms the other capacitor electrode.
4 more elements
In the process for fabricating a capacitor on the oxide layer associated with a monolithic silicon integrated circuit, the steps:
- depositing a first conductive layer on said integrated circuit, said first conductive layer being composed of a material selected from the group consisting of refractory metals and refractory metal silicides;
- photolithographically etching said first conductive layer to delineate said capacitor;
- depositing a first dielectric layer to cover said first conductive layer;
- depositing a second conductive layer over said first dielectric layer, said second conductive layer being composed of a material selected from the group consisting of refractory metals and refractory metal silicides;
- photographically etching said second conductive layer so as to cause said second conductive layer to form a plate that substantially overlaps said first conductive layer and is offset therefrom so as to expose at least a portion of said first conductive layer;
- depositing a second dielectric layer to cover said second conductive layer;
- photolithographically etching said second dielectric layer to create exposed areas of both said first and said second conductive layers;
- depositing a metal layer over said second dielectric layer whereby contact is made to both said first and second conductive layers;
- and
- photolithographically etching said metal layer whereby said metal layer makes contact to said first conductive layer in said exposed portion and to said second conductive layer in said offset portion.
7 more elements
Dependencies are inferred from the claim text.