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US 4,729,008 AGranted
High voltage IC bipolar transistors operable to BV.sub.CBO and method of fabrication
AssigneeHarris Corporation
InventorJames D. Beasom
Life of this patent
Estimating the term…
Abstract
A high voltage bipolar and JFET have their gate and base connected and source and collector connected and the appropriate geometry for the bipolar to operate to its BV.sub.CBO limit. The collector and channel regions have the same depth and impurity concentration, the base and top gate regions have the same depth and impurity concentration and the emitter and source and drain regions have the same depth and impurity concentration.
Claims14
An integrated circuit including bipolar and junction field effect transistors comprising:
- an N substrate;
- a PNP bipolar transistor in said substrate having a collector, base and emitter region;
- a P channel junction field effect transistor in said substrate having a channel region of the same depth and impurity concentration as said PNP collector region, source and drain regions of the same depth and impurity concentration as said PNP emitter region, a top gate region of the same depth and impurity concentration as said PNP base region and extending laterally beyond said channel region into said substrate and a buried N bottom gate region in said substrate of a high impurity concentration than said substrate and extending laterally beyond said channel region into said substrate to be connected to said top gate region by said substrate;
- and
- means for connecting said top gate and said base regions and means for connecting said source and said collector regions.
2 more elements
An integrated circuit including bipolar and junction field effect transistors comprising:
- an N substrate;
- an NPN bipolar transistor in said N substrate having a collector, base and emitter region;
- a PNP bipolar transistor in said substrate having a collector, base and emitter region;
- an N channel junction field effect transistor in said substrate having a channel region of the same depth and impurity concentration as said NPN collector region, source and drain regions having the same depth and impurity concentration as said NPN emitter region, a top gate having the same depth and impurity concentration as said NPN base region and extending laterally beyond said channel region, a buried P bottom gate region in said substrate extending laterally beyond said channel region and a lateral P region laterally surrounding said channel region and having the same depth and impurity concentration as said PNP collector region and connecting said top and bottom gate regions by a lower impurity region;
- and
- means for connecting said top gate and said base regions and means for connecting said source and said collector regions.
3 more elements
A bipolar transistor structure capable of operating to VB.sub.CBO comprising:
- a bipolar transistor having a base of a first conductivity type and an emitter and a collector of a second conductivity type opposite said first conductivity type;
- a junction field effect transistor having a top and bottom gate of said first conductivity type and a source, drain and channel of said second conductivity type;
- said channel and said collector have the same depth and impurity concentration and said top gate and said base have the same depth and impurity concentration;
- a connection region laterally encompassing said channel of said first conductivity type and lower impurity concentration than said gates, and extending from said bottom gate to a top surface adjacent said top gate;
- said gate being connected to said base and said source being connected to said collector.
2 more elements
An integrated circuit including bipolar transistors and junction field effect transistors comprising:
- a bipolar transistor including a collector region of a first depth, impurity concentration and conductivity type, a base region in said collector region of a second depth, impurity concentration and conductivity type, and an emitter region in siad base region of a third depth and impurity concentration and of said first conductivity type;
- a junction field effect transistor including a channel region of said first depth, impurity concentration and conductivity type;
- separate source and drain regions in said channel region of said third depth and impurity concentration and said first conductivity type;
- a top gate region in said channel region separating said source and drain regions of said second depth, impurity concentration and conductivity type;
- a buried bottom gate region of said second conductivity type and fourth impurity concentration;
- and a connecting region of said first conductivity type and a lower impurity concentration than said gates, laterally encompassing said channel region and extending from said bottom gate to a top surface adjacent said top gate;
- and
- means for connecting said gate regions to said base region and means for connecting said source region to said collector region.
5 more elements
Dependencies are inferred from the claim text.