US 4,729,006 AGranted

Sidewall spacers for CMOS circuit stress relief/isolation and method for making

AssigneeInternational Business Machines Corporation

InventorsAnthony J. Dally, Seiki Ogura, Jacob Riseman, Nivo Rovedo

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Abstract

A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

Claims15

Dependent claims

Fully isolated semiconductor regions for the manufacture of integrated circuits, comprising:

a substrate of doped semiconductors of a first conductivity type;
a plurality of trenches formed in designated areas of said substrate, and said trenches having a bottom, corners, and substantially vertical sidewalls, wherein said sidewalls form the walls of mesas, said mesas having a top surface;
sidewall spacers disposed on selected sidewalls which form mesas wich have been designated as mesas wherein channel devices of the opposite conductivity type to said first conductivity type are to be formed and on a portion of said trench bottoms adjacent to said selected sidewalls, said sidewall spacers being comprised of an insulating material doped to have a low viscosity at an elevated temperature with a dopant having said first conductivity type, said spacers extending along the designated sidewalls with their greatest thickness at the trench bottoms;
an insulation material with a viscosity at said elevated temperature greater than the viscosity of said sidewall spacer doped material, said insulation material disposed to fill said trenches up to said top surface of said mesas;
and
channel stops of said first conductivity type formed in said selected sidewalls of said designated mesas and formed around said trench corner and below said sidewall spacers by means of diffusion of said dopant of said first conductivity type from said sidewall spacers;
wherein said sidewall spacers reduce the occurrence of cracks in the insulator material filling said trenches by relieving internal mechanical stress therein thereby permitting deeper trenches, and allow the formation of channel stops via diffusion thereby permitting said mesa sidewalls to be substantially vertical.

4 more elements

Fully isolated semiconductor regions for the manufacture of CMOS integrated circuits, comprising:

a substrate of a P- epi-layer disposed on P+ silicon;
a plurality of trenches formed in predetermined areas of said substrate, said trenches having a bottom, corners, and substantially vertical sidewalls, wherein said sidewalls form the walls of mesas, said mesas having a top surface;
sidewall spacers of borosilicate glass doped to 2-15 wt % formed only on selected sidewalls which form mesas which have been designated to have N-channel devices formed therein, and on a portion of said trench bottoms adajcent to said selected sidewalls, said spacers extending along the designated sidewalls with their greatest thickness at the trench bottoms;
SiO.sub.2 disposed to fill said trenches up to said top surface of said mesas;
channel stops of P conductivity type formed in said selected sidewalls of said designated N-channel mesas and formed around said trench corners and below said sidewall spacers by means of diffusion of the dopant from said borosilicate glass from said sidewall spacers;
and
means defining a field effect transistor having source, drain, and channel regions, on a plurality of said designated mesas, wherein said channel region is disposed in the mesa to extend between said source and drain regions, and said source and drain regions are adjacent respective channel stops;
wherein said sidewall spacers reduce the occurrence of cracks in the SiO.sub.2 filling said trenches by relieving internal mechanical stress therein thereby permitting deeper trenches, and allow the formation of channel stops via diffusion thereby permitting said mesa sidewalls to be substantially vertical.

5 more elements

Dependencies are inferred from the claim text.