MIS controlled gate turn-off thyristor
AssigneeKabushiki Kaisha Toshiba
InventorsTakashi Shinohe, Katsuhiko Takigami, Hiromichi Ohashi, Akio Nakagawa
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Abstract
An MIS controlled gate turn-off thyristor includes a pnpn structure comprised of a first emitter layer, a first base layer, a second base layer and a second emitter layer, and a turn-off MIS transistor for short-circuiting the second base layer to the second emitter layer. A low impurity concentration layer is formed on the second base layer and the second emitter layer is so formed that it extends, through the low impurity concentration layer, into the second base layer. The MIS transistor is formed on the surface portion of said low impurity concentration layer.
Claims11
An MIS controlled gate turn-off thyristor comprising:
- a first emitter layer of a first conductivity type;
- a first base layer of a second conductivity type forming a pn junction relative to the first emitter layer;
- a second base layer of the first conductivity type forming a pn junction relative to the first base layer;
- a low impurity concentration layer formed on the second base layer;
- a second emitter layer of the second conductivity type formed such that it extends, through the low impurity concentration layer, into the second base layer;
- first and second ohmic electrodes in contact with the first and second emitter layers, respectively;
- and
- an MIS transistor formed in the surface portion of the low impurity concentration layer and having source and drain regions, one of which is connected to the second ohmic electrode and the other of which is connected through a low resistance layer to the second base layer to allow the second base layer to be short-circuited to the second emitter layer.
Dependencies are inferred from the claim text.