Frequency divide by N circuit
AssigneeTexas Instruments Incorporated
InventorMark A. Stambaugh
Life of this patent
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Abstract
A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency "f" into two non-overlapping complementary clock signals of frequency "f" and a shift register circuit. The shift register circuit is coupled to the signal splitting means and generates an output clock signal of frequency f/n in response to the two complementary clock signals. The output clock signal has a duty cycle equal to ((n-1)/2+D.sub.in)/n where D.sub.in is the duty cycle of the incoming clock signal. The output duty cycle is substantially independent of processing and operating conditions.
Claims14
A frequency divide by n circuit, where n is an odd integer, comprising:
- means for splitting an incoming clock signal of frequency "f" into a first and a second clock signal, said first and second clock signals being nonoverlapping and complementary relative to one another, and having a frequency "f";
- a shift register circuit comprising:
- a first stage, having a pass gate therein which is controlled by said first complementary clock signal;
- a second stage, having a pass gate therein which is controlled by said second complementary clock signal;
- a plurality of intermediate stages, each of said intermediate stages having a pass gate therein which is controlled by one of said complementary clock signals, said intermediate stages connected in a series with said first and second stages with first and second complementary clock signals controlling pass gates in alternating stages;
- and
- feedback logic having a first input connected to said second stage, having a second input connected to an intermediate stage in said series, and having an output connected to said first inverting stage, for providing a feedback signal to said first inverting stage, said feedback signal having a frequency of f/n;
- and
- output logic, having a first input connected to one of said intermediate stages, and having a second input connected to an adjacent one of said intermediate stages, so that the output signal of said output logic has a frequency of f/n and a duty cycle corresponding to that of said incoming clock signal.
A frequency divide by 3 circuit, comprising:
- an input driver circuit couplable to an input clock signal of frequency "f";
- means for splitting said clock signal into a pair of complementary non-overlapping clock signals of frequency "f";
- a shift register circuit coupled to said splitting means for generating an output clock signal of frequency f/3 in response to said two complentary clock signals comprising:
- a series of four inverting stages, each inverting stage having an inverter and a pass gate therein, said pass gates in the first and third of said inverting stages controlled by a first one of said complementary clock signals, said pass gates in the second and fourth of said inverting stages controlled by a second one of said complementary clock signals;
- feedback logic having a first input connected to said second inverting stage and second input connected to said fourth inverting stage, and having an output connected to said first inverting stage for providing to said first inverting stage a feedback signal of frequency f/3;
- and
- output logic having a first input connected to said second inverting stage and a second input connected to said third inverting stage, for presenting at its output a signal having a frequency of f/3 and a duty cycle corresponding to the duty cycle of said input clock signal;
- and
- an output buffer coupled to the output of said output logic of said shift register circuit.
Dependencies are inferred from the claim text.