Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits

A programmable macrocell in an integrated circuit device comprising:

• architecture control means including a plurality of architecture control circuits each having
• a programmable EPROM device including gate, drain and source electrodes which when programmed generates a logic signal of a first state and when unprogrammed generates a logic signal of a second state,
• read and write control means connected to said EPROM device and responsive to an input program data signal and a corresponding address signal and operative to program said EPROM device by applying a programming potential thereto, and
• sense means connected to said EPROM device for sensing the programmed or unprogrammed state of said EPROM device and for developing a commensurate control signal;
• and
• electronic circuit means responsive to said control signals and operative to perform particular operations selected by said control signals on input data signals and to develop commensurate output data signals, said electronic circuit means including a digital multiplexer means having a plurality of AND gates each of which receives at least one input data signal and a control signal developed by said architecture control means, the outputs of said AND gates being ORed together in an output OR gate which in turn develops an output signal corresponding to one of said input data signals as selected by a particular one of said control signals.

An integrated circuit device comprising:

• electronic logic circuit means responsive to at least one control signal and operable to perform a particular logic function on at least one input data signal to generate at least one commensurate output signal;
• and
• programmable control means for causing said logic circuit means to have particular circuit configurations, and including:
• a first reprogrammable memory device which may be programed to generate either a logic signal of a first state or a logic signal of a second state;
• a first programming means connected to said first reprogrammable memory device and responsive to input program data signals and a corresponding address signal and operative to program said first reprogrammable memory device by applying a programming potential thereto;
• a first sense means connected to said first reprogrammable memory device for sensing the state of the logic signal generated by said first reprogrammable memory device and for developing a commensurate first control signal for controlling said logic circuit means.