Programmable, asynchronous logic cell and array
AssigneeConcurrent Logic, Inc.
InventorFrederick C. Furtek
Life of this patent
Estimating the term…
Loading patent…
AssigneeConcurrent Logic, Inc.
InventorFrederick C. Furtek
Estimating the term…
An asynchronous logic cell and a two- or three dimensional array formed of such cells. Each cell comprises a number of exclusive-OR gates, Muller C-elements and programmable switches. The logic cell is reprogrammable and may even be reprogrammed dynamically, such as to perform recursive operations or simply to make use of hardware which is temporarily idle. Programming is accomplished by setting the states of the switches in each cell. A user-friendly programming environment facilitates the programming of the switches. The array can be used to implement any circuit capable of being modelled as a broad class of Petri Nets. Configurations for (i.e., programs for setting cell switches to create) circuit blocks such as adders, multiplexers, buffer stacks, and so forth, may be stored in a library for future reference. With an adequate library, custom hardware can be designed by simply mapping stored blocks onto chips and connecting them together. Further, because the array is regular and switch settings can produce logical wires, crossovers, connections and routings running both "horizontally" and "vertically", it is in general possible to "wire around" defective elements. If a large wafer contains defective cells, those cells can simply be avoided and bypassed, with the remainder of the wafer remaining useful.
A digital logic cell comprising:
A digital logic cell comprising:
A homogeneous array of digital logic cells, each cell comprising (a) a set of exclusive-OR elements, each having two inputs and an output;
A digital logic cell for use in implementing Petri Nets, comprising:
An array of digital logic cells for use in implementing Petri Nets, comprising a plurality of cells each having (1) a set of disjunctive means of a single type, (2) a set of conjunctive means of a single type, and (3) a set of programmable configuration switches for selectively, operatively interconnecting disjunctive and conjunctive means;
An array of digital logic cells for use in implementing Petri Nets, comprising a plurality of cells each having (1) a set of disjunctive means of a single type, (2) a set of conjunctive means of a single type, and (3) a set of programmable configuration switches for selectively, operatively interconnecting disjunctive and conjunctive means;
A bipartite logic structure comprising a first set of nodes comprising conjunctive and disjunctive elements and a second set of nodes comprising means for selectively, operatively interconnecting the conjunctive and disjunctive elements;
Dependencies are inferred from the claim text.