Self-correcting frequency dividers
AssigneeAmerican Telephone and Telegraph Company, AT&T Bell Laboratories
InventorsRobert J. Bayruns, Harry T. Weston
Life of this patent
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Abstract
A frequency divider for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate or NAND gate, respectively, connected for delivering its output to an n-bit delay device, the NOR or NAND gate further connected for receiving the output of the delay device as feedback at one of its two-input terminals and for receiving the n-bit counting stream at the other of its two-input terminals. The output of the delay device is then a 2n-bit counting stream.
Claims24
In combination:
- (a) a source of an n-bit counting stream of period equal to nT, where n is an integer greater than unity;
- (b) a two-input NOR gate having one of its two input terminals connected for receiving the n-bit counting stream from the source;
- (c) a delay device having n serially connected stages each arranged for delaying bit flow therethrough by an amount of time equal to T, said delay device having its input terminal connected for receiving the output of the NOR gate and its output terminal directly connected to the other input terminal of the NOR gate, whereby the output terminal of the delay device develops a 2n-bit counting stream.
A self-correcting frequency divider circuit for converting an input n-bit counting stream having a periodicity equal to nT into an output 2n-bit counting stream having a periodicity equal to 2nT at a circuitry output terminal, where n is an integer greater than unity, comprising:
- (a) source means for supplying the n-bit counting stream, said stream being a periodic sequence of a single zero bit followed by (n-1) one bits, each bit being valid during a separate time slot of duration T;
- (b) a two-input NOR gate having one of its two input terminals connected to said source means, for receiving the input n-bit counting stream;
- and
- (c) a delay device for delaying bit flow therethrough by an amount of time equal to said nT having its input terminal directly connected to the output terminal of the NOR gate and its output terminal directly connected both to the other terminal of the NOR gate and to the frequency divider circuit output terminal, whereby the circuit output terminal delivers the output 2n-bit counting in response to the input n-bit counting stream.
A self-correcting frequency divider circuit for converting an input n-bit counting stream having a periodicity equal to nT into an output 2n-bit counting stream having a periodicity equal to 2nT at a circuitry output terminal, where n is an integer greater than unity, comprising:
- (a) source means for supplying the n-bit counting stream, said stream being a periodic sequence in which each period thereof consists of a single one bit followed by (n-1) zero bits, each bit being valid during a separate time slot of duration T;
- (b) a two-input NAND gate having one of its two input terminals connected to said source means, for recieving the input n-bit counting stream;
- and
- (c) a delay device for delaying bit flow therethrough by an amount of time equal to said nT having its input terminal directly connected to the output terminal of the NAND gate and its output terminal directly connected both to the other input terminal of the NAND gate and to the frequency divider circuit output terminal, whereby the circuit output terminal delivers the output 2n-bit counting stream in response to the input n-bit counting stream.
A self-correcting frequency divider circuit comprising:
- (a) a source of an n-bit counting stream of period equal to nT, where n is an integer greater than unity;
- (b) a two-input NAND gate having one of its two input terminals connected for receiving the n-bit counting stream from the source;
- (c) a delay device having n serially connected stages each arranged for delaying bit flow therethrough by an amount of time equal to T, said delay device having its input terminal connected for receiving the output of the NAND gate and its output terminal directly connected to the other input terminal of the NAND gate, whereby the output terminal of the delay device develops a 2n-bit counting stream.
A combination comprising:
- (a) a source of an n-bit counting stream of period equal to nT.
- (b) two-input logic means for producing an output representative of the inverse of one of its inputs when the other of its inputs has a first binary digital value and for producing an output which is equal to said first binary digital value whenever the other of its inputs is equal to the inverse of the first binary digital value, said logic means having one of its input terminals connected for receiving the n-bit counting stream from the source;
- and
- (c) a delay device having n serially connected stages each arranged for delaying bit flow therethrough by an amount of time equal to T, said delay device having its input terminal connected for receiving the output of the logic means and having its output terminal connected for delivering its output to the other input terminal of the logic means, whereby the output terminal of the delay device devleops a 2n-bit counting stream;
- and
- (d) utilization means connected for receiving the 2n-bit counting stream and adapted for utilizing said 2n-bit counting stream.
Dependencies are inferred from the claim text.