Sense circuit with presetting means
AssigneeRCA Corporation
InventorDouglas S. Piasecki
Life of this patent
Estimating the term…
Abstract
A circuit whose output is asymmetrical whereby the circuit makes a transition from a first state to a second state more slowly than from the second state to the first state a preset towards the second state prior to the application of data input signals to the circuit.
Claims8
The combination comprising:
- a flip-flop having set and reset inputs and first and second complementary outputs, said flip-flop being characterized in that its outputs are driven from a first state to a second state more slowly than from the second state to the first state and said flip-flop being further characterized in that there is significantly more capacitance associated with one output than with the other;
- and
- a selectively enabled differential amplifier having first and second inputs coupled to receive binary input signals, and having a first output connected to said set input and a second output connected to said reset input;
- said differential amplifier, when enabled and in the absence of input signals, including means for driving said one output of said flip-flop towards said second state when the voltages applied to its first and second inputs are approximately equal.
In a circuit having an output and which includes a storage means which in response to an input signal of one binary significance drives said output to a first state and which in response to an input signal of the other binary significance drives said output to a second state and where the output drive of the circuit is asymmetrical whereby the transition from the first state to a second state tends to be slower than the transition from the second state to the first state, the improvement comprising:
- differential amplifying means coupled to said storage means for presetting the circuit towards the second state prior to the application of said input signals to the circuit.
Dependencies are inferred from the claim text.