Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer
AssigneeSolid State Scientific Corporation
InventorsAlexander H. Owens, Mark A. Halfacre, David S. Pan
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Abstract
A CMOS EPROM is made wherein the typical EPROM device is an N-channel IGFET having a control gate self-aligned with an underlying floating gate. In this process the EPROM floating gate and the gates of both the P-channel and N-channel peripheral circuit transistors are formed from a first deposited polysilicon layer. The EPROM control gate is formed from a second deposited polysilicon layer. This CMOS EPROM process employs a surprisingly few photoresist steps and is compatible with a high temperature oxidation step for making a very high quality intergate polysilicon oxide in the EPROM devices.
Claims14
A method of fabricating on a P-conductivity type substrate at least one each of an EPROM device having self-aligned floating and control gates, a P-channel transistor device, and an N-channel transistor device comprising the steps of:
- (a) forming an N-well in said substrate encompassing a region in which said P-channel device is to be formed and implanting P-type impurity atoms in regions of said substrate at which said EPROM, P-channel and N-channel devices, respectively, are to be formed to simultaneously introduce the last impurities that will determine the threshold voltages, respectively, of each of said three devices;
- (b) forming a first polysilicon layer over said substrate without intervening doping steps after said implanting;
- (c) oxidizing the outer surface of said first polysilicon layer to grow a polysilicon oxide insulating layer thereover;
- (d) removing initial portions of said first polysilicon layer to leave one remaining portion over said EPROM region, and two other remaining portions that occupy a central region over each of said N-channel and P-channel device regions, respectively, to form the gates of said N-channel and P-channel devices;
- (e) forming a second polysilicon layer over said insulating layer and said EPROM device region;
- and
- (f) forming an EPROM-gates masking layer over said second polysilicon layer and a central part of said EPROM region, and removing the adjacent exposed portions of said first and second polysilicon layers not covered by said EPROM-gates masking layer to form said EPROM self-aligned gates.
Dependencies are inferred from the claim text.