US 4,645,951 AGranted

Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals

AssigneeHitachi, Ltd.

InventorAkira Uragami

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor integrated circuit is provided which combines an MOS internal logic circuit (C-MOS in the preferred embodiment) with input and output buffers which have pin-compatibility with ECL circuitry. An ECL-CMOS level-conversion input buffer circuit arranged for a C-MOS internal logic circuit has a pair of emitter-coupled transistors which are responsive to an input signal at an ECL level. Thus, the input buffer circuit operates at a high speed. A CMOS-ECL level-conversion output buffer circuit arranged for the C-MOS internal logic circuit has an amplifying transistor, which has its base responsive to the output signal of the C-MOS internal logic circuit, and an emitter-follower transistor which has its base responsive to the collector signal of said amplifying transistor for generating an output signal at an ECL level at its emitter. Thus, the output buffer circuit operates at a high speed. Utilizing such an arrangement, the circuit can obtain the benefits of lower power consumption for the C-MOS internal logic circuit together with high speed in the buffer stages and ECL compatibility.

Claims14

Dependent claims

A semiconductor integrated circuit comprising:

(1) an internal logic block including a plurality of C-MOS elements;
(2) an input terminal;
(3) an output buffer circuit connected between said internal logic circuit and said output terminal;
(4) a first power source terminal receptive of a ground potential as a first power source voltage;
and
(5) a second power source terminal receptive of a negative voltage as a second power source voltage,
wherein said internal logic circuit and said output buffer circuit are operative with said negative voltage, wherein said output buffer circuit has an input terminal receptive of an output signal of said internal logic circuit, wherein said output buffer circuit includes means for generating an output signal at an ECL level at said output terminal in response to receiving the output signal of said internal logic circuit, wherein said means of said output buffer circuit includes an emitter-follower transistor having its emitter connected with said output terminal and its base responsive to the output signal of said internal logic circuit as well as a semiconductor amplifying element having its input electrode responsive to the output signal of said internal logic circuit and its output electrode connected through a load resistor with said ground potential so that the base of said emitter-follower transistor is driven by the signal of said output electrode of said semiconductor amplifying element, wherein said means of said output buffer circuit further comprises a second emitter-follower transistor having its emitter coupled with a second output terminal and its base coupled with a second semiconductor amplifying element, wherein said second semiconductor amplifying element is differentially coupled with said first semiconductor amplifying element, and wherein said first and second semiconductor amplifying elements comprise a pair of MOS transistors.

4 more elements

A semiconductor integrated circuit comprising:

(1) an internal logic block including a plurality of C-MOS elements;
(2) an output terminal;
(3) an output buffer circuit connected between said internal logic circuit and said output terminal;
(4) a first power source terminal receptive of a ground potential as a first power source voltage;
and
(5) a second power source terminal receptive of a negative voltage as a second power source voltage,
wherein said internal logic circuit and said output buffer circuit are operative with said negative voltage, wherein said output buffer circuit has an input terminal receptive of an output signal of said internal logic circuit, wherein said output buffer circuit includes means for generating an output signal at an ECL level at said output terminal in response to receiving the output signal of said internal logic circuit, wherein said means of said output buffer circuit includes an emitter-follower transistor having its emitter connected with said output terminal and its base responsive to the output signal of said internal logic circuit as well as a semiconductor amplifying element having its input electrode responsive to the output signal of said internal logic circuit and its output electrode connected through a load resistor with said ground potential so that the base of said emitter-follower transistor is driven by the signal of said output electrode of said semiconductor amplifying element, wherein said means of said output buffer circuit further comprises a second emitter-follower transistor having its emitter coupled with a second output terminal and its base coupled with a second semiconductor amplifying element, wherein said second semiconductor amplifying element is differentially coupled with said first semiconductor amplifying element, wherein said internal logic circuit provides first and second output signals to said output buffer circuit, and wherein said output buffer circuit includes a first switching element coupled between said first internal logic output signal and said first semiconductor amplifying element and a second switching element coupled between said second internal logic output signal and said first semiconductor amplifying element.

4 more elements

A semiconductor integrated circuit comprising:

(1) an internal logic block including a plurality of C-MOS elements;
(2) an output terminal;
(3) an output buffer circuit connected between said internal logic circuit and said output terminal;
(4) a first power source terminal receptive of a ground potential as a first power source voltage;
and
(5) a second power source terminal receptive of a negative voltage as a second power source voltage,
wherein said internal logic circuit and said output buffer circuit are operative with said negative voltage, wherein said output buffer circuit has an input terminal receptive of an output signal of said internal logic circuit, wherein said output buffer circuit includes means for generating an output signal at an ECL level at said output terminal in response to receiving the output signal of said internal logic circuit, wherein said means of said output buffer circuit includes an emitter-follower transistor having its emitter connected with said output terminal and its base responsive to the output signal of said internal logic circuit as well as a semiconductor amplifying element having its input electrode responsive to the output signal of said internal logic circuit and its output electrode connected through a load resistor with said ground potential so that the base of said emitter-follower transistor is driven by the signal of said output electrode of said semiconductor amplifying element, wherein said means of said output buffer circuit further comprises a second emitter-follower transistor having its emitter coupled with a second output terminal and its base coupled with a second semiconductor amplifying element, wherein said second semiconductor amplifying element is differentially coupled with said first semiconductor amplifying element, wherein said first and second semiconductor amplifying elements comprise a pair of emitter-coupled bipolar transistors, wherein said output buffer circuit further includes first and second switching elements of MOS transistors as well as an inverter circuit, wherein said first switching element is responsive to the output signal of said internal logic circuit and coupled between said input electrode and said output electrode of said first semiconductor amplifying element, wherein an input terminal of said inverter circuit is responsive to the output signal of said internal logic circuit, and wherein said second switching element is responsive to an output signal of said inverter circuit and coupled between an input electrode and an output electrode of said second semiconductor amplifying element.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/646,110Filed 31 Aug 1984
Priority: JP 58-15781731 Aug 1983
Granted: 24 Feb 1987
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H03K 19/01812
Interface arrangements: with at least one differential stage
H03K 19/017527
Using a combination of bipolar and field effect transistors [BIFET]: with at least one differential stage
H03K 19/09448
Using MOSFET or insulated gate field-effect transistors, i.e. IGFET: in combination with bipolar transistors [BIMOS]
H10W 72/90
Interconnections or connectors in packages: bond pads, in general

Family

No related US applications are recorded in the indexed filing history.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key