Bus differential relay

In a power system network including a bus section and a plurality of feeder lines coupled thereto for conducting alternating current through said bus section, each feeder line including a current transformer for measuring the alternating current therethrough and generating a signal representative thereof in both amplitude and periodicity, each current transformer having a limited current amplitude measurement capacity beyond which saturation thereof occurs resulting in the loss of its generated feeder line current signal during saturation, a bus differential relay governed by said generated current signals of said plurality of feeder lines to protect said bus section from an internal fault by interrupting current through said plurality of feeder lines and to safeguard against current interruption from a false indication of an internal fault caused by an external fault on at least one of the feeder lines of said plurality with the corresonding current transformer being saturated during a portion of the periods of said alternating current, said bus differential relay comprising:

• first circuit means for summing instantaneously the generated current signals corresponding to the feeder lines coupled to said bus section and for generating a current differential signal representative of said instantaneous current signal sum;
• second circuit means for generating two reference amplitude levels which form an amplitude window;
• third circuit means for generating a first indication upon the occurrence of the amplitude of said current differential signal extending outside said formed amplitude window and for generating a second indication upon the occurrence of the amplitude of said current differential signal falling within said formed amplitude window;
• first timing circuit set by a first indication generation to commence timing over a first time period and, after timing through said first time period, to generate a trip signal to render current interruption through said plurality of feeder lines;
• and
• second timing circuit set by a second indication generation to commence timing over a second time period and, after timing through said second time period, to generate a reset signal, said second timing circuit being resettable during said second timing period by a first indication generation to prevent the generation of said reset signal, said first timing circuit being resettable during said first timing period by a reset signal generation to prevent the generation of said trip signal, said first timing period being longer than said second timing period.