A backup power switching circuit comprising:
- at least first, second, third, fourth, fifth, and sixth p-channel MOS transistors, each of said transistors including a control electrode, an output electrode, an input electrode;
- and a substrate;
- at least first, second, third, fourth, and fifth n-channel MOS transistors, each of said transistors including a control electrode, an output electrode, an input electrode, and a substrate;
- a high resistive impedance;
- a reference terminal, adapted to provide a reference potential;
- a first input terminal, coupled to the input electrode of said first p-channel MOS transistor, and to the control electrode of said first n-channel MOS transistor;
- a second input terminal, coupled to the input electrode of said second p-channel MOS transistor, and to the control electrode of said second n-channel MOS transistor;
- an output terminal, coupled to the output electrodes of said first and second p-channel MOS transistors;
- means for applying a first direct current potential to said first input terminal;
- means for applying a second direct current potential to said second input terminal, said second direct current potential having the same polarity relative to said reference terminal as said first direct current potential;
- and
- coupling means for coupling said transistors and said terminals wherein:
- (a) the control electrode of said first p-channel MOS transistor is coupled to the output electrode of said fifth p-channel MOS transistor and to the input electrode of said fourth n-channel MOS transistor, and the control electrode of said second p-channel MOS transistor is coupled to the output electrode of said sixth p-channel MOS transistor and to the input electrode of said fifth n-channel MOS transistor;
- (b) said first and second n-channel MOS transistors have their substrates coupled together and to said reference terminal, providing a reverse bias with respect to their respective input electrodes, and their output electrodes are together coupled through said high resistive impedance to the input electrode of said third n-channel MOS transistor and to the control electrodes of said third and fourth n-channel MOS transistors;
- (c) the output electrodes of said third and fourth n-channel MOS transistors are jointly coupled to said reference terminal and to the output electrode of said fifth n-channel MOS transistor;
- (d) the input electrode of said first n-channel MOS transistor is coupled to the output electrode of said third p-channel MOS transistor and to the control electrodes of said third and fourth p-channel MOS transistors;
- (e) the input electrode of second second n-channel MOS transistor is coupled to the output electrode of said fourth p-channel MOS transistor and to the control electrode of said fifth p-channel MOS transistor;
- (f) the input electrodes of said third and fourth p-channel MOS transistors are coupled to the output electrode of said first p-channel MOS transistor, to said output terminal, and to the input electrodes of said fifth and sixth p-channel MOS transistors;
- and
- (g) the output electrode of said fifth p-channel MOS transistor and the input of electrode of said fourth n-channel MOS transistor are further coupled to the control electrodes of said sixth p-channel MOS transistor and said fifth n-channel MOS transistor;
- wherein, in dependence on the relative magnitudes of the direct current potentials applied to said first and second input terminals, said first or said second p-channel MOS transistor is driven into conduction to couple said input terminal having the greater magnitude to said output terminal.