Power on/off reset generator
AssigneeWerkzeugmaschinenfabrik Oerlikon-Buehrle AG
InventorPeter A. Miller
Life of this patent
Estimating the term…
Abstract
A power on-off reset generator for monitoring a power supply for a logic system powered from the monitored power supply. A precision-voltage sensor produces a control signal for a time delay circuit when the power supply rises above a preselected value. A delay signal is generated which maintains an active-LOW control signal to the logic system and causes a Schmitt trigger circuit to produce a HIGH control signal to the logic system at the end of the delay signal.
Claims12
A power on-off reset generator for monitoring a power supply for a controlled logic system comprising:
- voltage sensor means connected in parallel with said power supply for producing an output signal when the voltage of said power supply rises above a preselected value;
- time delay means connected to receive the output signal from said voltage sensor means for producing a delay signal of a preselected duration;
- trigger circuit means connected to said time delay means and responsive to the termination of said delay signal for producing a bounce-free enabling logic level reset signal, said trigger circuit producing a disabling logic level signal when said power supply voltage is less than said preselected value;
- and
- output driver means associated with said trigger circuit for furnishing said enabling signal and said disabling signal in a power fail-safe manner to said controlled logic system,
- each of said voltage sensor means, time delay means, trigger circuit means, and output driver means employing saturation mode circuit design principle and operating from the same power supply being monitored, and performing properly under a range of normal and subnormal power supply conditions, said range of power supply conditions for proper operation spanning from the selected nominal operating voltage of said power supply, down to 1.0 volts guaranteed, 0.7 volts typical.
A power on-off reset generator utilizing single base-emitter drop saturation mode principle for monitoring a power supply and controlling a logic system to be enabled when the power supply voltage is greater than a value E.sub.T and to be actively disabled when the power supply voltage is less than E.sub.T comprising:
- a first differential amplifier powered by said power supply and having a first input connected to a reference voltage divider across said power supply, said voltage divider having a resistor R.sub.1 and a resistor R.sub.2 whereby a reference voltage equal to (R.sub.1 /R.sub.1 +R.sub.2) times the power supply voltage is produced, a second input, and an output;
- a temperature compensated precision-voltage zener diode connected from said second input of said first differential amplifier to said power supply whereby said first differential amplifier produces an output signal when the power supply voltage is equal to or greater than the breakdown voltage of said zener diode divided by ##EQU2## a time delay capacitor connected to said power supply via a charging resistor;
- a discharge transistor having an output connected in parallel with said capacitor and an input connected to said output of said first differential amplifier;
- a second differential amplifier having a first input thereof connected to said capacitor, a second input connected to said first input of said first differential amplifier, and an output thereof;
- and
- a driver transistor having an input connected to said output of said second differential amplifier and an output connected to said logic system, said output also connected in positive feedback relationship to said first input of said second differential amplifier, whereby said driver transistor produces an active-LOW output when the power supply voltage is less than E.sub.T and a HIGH output when the power supply is equal to or greater than E.sub.T, such use of saturation mode principle making satisfactory operation possible, even when the power supply voltage is down as low as one volt.
Dependencies are inferred from the claim text.