Remote multiplexer terminal with redundant central processor units
AssigneeAvco Corporation
InventorsJames R. Long, Roy L. Harrill
Life of this patent
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AssigneeAvco Corporation
InventorsJames R. Long, Roy L. Harrill
Estimating the term…
An approach is disclosed for accomplishing redundancy in the central processor units of a remote multiplexer terminal (RMT). Through execution of a stored software program the RMT receives data from input/output devices, processes that data and transmits it to external equipment. The system uses two central processor units (CPU's), each with its own input/output (I/O) bus. Both CPU's actively and continuously monitor the status of the I/O subsystems. The software program designates one CPU as the "Master", the other CPU as the "Slave". The CPU designated as "Master" performs active control functions so long as error detection circuitry within each CPU determines that the operational status of the "Master" is good. Error detection is accomplished by incorporation of a "Watch Dog Timer" in each CPU. A failing CPU is redesignated to be a Slave (and is halted) and the previously designated Slave CPU is redesignated as a Master. Since it has been "shadowing" the old Master CPU, the new Master CPU has a current record of the status of the I/O subsystems stored in its memory. Using this data, the new Master CPU assumes control over all of the I/O functions that were previously being controlled by the old Master CPU. No physical switchover occurs - only a software failover.
Apparatus for providing a remote multiplexer terminal with a failover capability from a first central processor unit to a second central processor unit without loss of data, said remote multiplexer terminal being a data acquisition and control system capable of receiving data at a clocked rate from a multiplicity of input/output devices and after processing that data according to a software program, delivering the results to an external equipment, the software program additionally serving to designate the first central processor unit as the "Master" and the second central processor unit as the "Slave", the apparatus being integral with the central processor units and comprising:
The invention as defined in claim 3 wherein the microprocessor is a 16 bit unit.
Dependencies are inferred from the claim text.