Clocked latching circuit
AssigneeAT&T Bell Laboratories
InventorRobert M. Paski
Life of this patent
Estimating the term…
Abstract
A digital latching circuit includes a quantizer having an input pair of emitter-coupled transistors connected with output transimpedance circuits. The quantizer is responsive to the state of an input signal applied to the input pair for producing from the output transimpedance circuits a quantized output signal. A feedback pair of emitter-coupled transistors is interposed between the outputs of the transimpedance circuits and the inputs to the transimpedance circuits. Current pulses are applied alternatively to the common emitter circuits of the input pair and the feedback pair of transistors for alternatively enabling the quantizing of the state of the input signal and the latching of that quantized state.
Claims6
A digital latching circuit comprising
- a quantizer having an input pair of emitter-coupled transistors of a first conductivity type connected to output transimpedance circuits, each of said output transimpedance circuits having an input and an output and including transistors of a second conductivity type, the quantizer being responsive to the state of an input signal applied to the input pair of producing from the output transimpedance circuits a quantized output signal,
- a feedback pair of emitter-coupled transistors of the first conductivity type, each one of said feedback transistors being interposed between the output of a respective one of said transimpedance circuits and the input of that same transimpedance circuit for coupling output signals of that transimpedance circuit to the input of that same transimpedance circuit, and
- a clock source for applying clock current pulses alternatively to the coupled emitter circuits of the input pair and of the feedback pair for alternatively enabling the quantizing of the state of the input signal and the latching of that quantized state.
A digital latching circuit for quantizing and latching the quantized values present in an output signal, said circuit comprising
- first and second pairs of emitter-coupled transistors each transistor of which is of a first conductivity type and has emitter, base, and collector electrodes;
- means for coupling said input signal to the base electrodes of said first pair of emitter-coupled transistors;
- a pair of transimpedance circuits each one of which has an input and an output and a transistor of opposite conductivity type;
- means for coupling each collector electrode of said first pair of emitter-coupled transistors to a different collector electrode of said second pair of emitter-coupled transistors and to the input of a different transimpedance circuit;
- means for coupling the output of each of said pair of transimpedance circuits to the base electrode of the respective transistor of said second pair of emitter-coupled transistors to which its input is connected;
- and
- a clock source for applying clock current pulses alternately to the emitter electrodes of said first pair of emitter-coupled transistors and to the emitter electrodes of said second pair of emitter-coupled transistors, thereby causing the digital latching circuit to alternately quantize said input signal and latch the quantized value.
Dependencies are inferred from the claim text.