Contactless tite RAM
AssigneeTexas Instruments Incorporated
InventorsPallab Chatterjee, Hisashi Shichijo, John E. Leiss
Life of this patent
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Abstract
A transversly injected quasi-floating gate memory cell. A memory transistor in bulk silicon has a channel region in bulk silicon which is capacitatively coupled both to a thin polysilicon quasi-floating gate and to an overlying word line. The thin polysilicon level which comprises the floating gate is not coterminous with the channel region of the memory transistor, but the quasi-floating gate portion of the thin polysilicon layer is connected, through a polysilicon channel region, to a write bit line. The overlying word line thus addresses both the write transistor in a thin polysilicon level and also the memory transistor itself in the substrate.
Claims6
A memory cell comprising:
- a semiconductor substrate;
- a read bit line in said substrate having a second conductivity type;
- a drain voltage line in said substrate having a second conductivity type;
- a memory transistor channel region at the surface of said substrate, separating said read bit line from said drain voltage line;
- a word line defining a gate above and capacitatively coupled to said memory transistor channel region;
- and
- a thin polysilicon layer, said thin polysilicon layer comprising a quasi-floating gate portion thereof interposed between said word line and said channel region of said memory transistor and capacitatively coupled both to said word line and said channel region of said memory transistor, and said thin polysilicon layer also comprising a polysilicon channel region, said thin polysilicon channel region comprising a dopant concentration which is less than 10.sup.19 per cubic cm, said thin polysilicon channel region being capacitatively coupled to said word line, and said thin polysilicon layer also comprising a heavily doped write bit line portion, said polysilicon channel portion of said thin polysilicon layer being interposed between said write bit line portion and said quasi-floating gate portions respectively of said thin polysilicon layer, said quasi-floating gate having said second conductivity type.
Dependencies are inferred from the claim text.