Testing method and structure for leakage current characterization in the manufacture of dynamic RAM cells

Apparatus for testing integrated circuits to determine or measure significant leakage currents comprising:

• a testing structure within a semiconductor wafer, said structure including at least two gate-controlled diodes, the individual gates of which have markedly different perimeter-to-area ratios, and (2) an additional metallurgical junction common to said at least two gate-controlled diodes, said individual gates overlying one of said gate-controlled diodes and said common junction respectively;
• a voltage source, and means for connecting said voltage source to said two gate-controlled diodes and said common junction;
• means for testing each of said gate-controlled diodes by alternately varying the gate voltage applied to one of said two diodes while maintaining the gate of the other diode at an appropriately low potential, so as to obtain the relationship between reverse current and gate voltage for each diode whereby the perimeter contributed leakage current component is separated from the area contributed component.