Scannable asynchronous/synchronous CMOS latch

A scannable synchronous/asynchronous CMOS latch circuit comprising:

• a first latch circuit for latching a first output signal to a first level in response to a prescribed change in a data input signal applied to a first input terminal thereof, said first output signal being connected to a first output terminal and for latching the first output signal to a second level in response to the application of a reset signal applied to a reset terminal thereof, said latching characterized by occurring without reference to any clocking signals;
• a second latch circuit connected to receive said data input signal from said first latch circuit and to latch a second output signal to a signal equivalent to the level of said data input signal immediately prior to the occurrence of a specified transition in a first clock signal applied to a clock terminal of said scannable synchronous/asynchronous CMOS latch circuit, and to maintain the latch level of said second output signal for the entire duration of cycle of said first clock signal said second output signal being connected to a second output terminal;
• scanning means for selectively shifting data held in said second latch circuit to a third output terminal;
• input means for selectively shifting data applied to a second input terminal of said scannable synchronous/asynchronous CMOS latch circuit directly into said second latch circuit;
• and
• select means, responsive to control signals including said first clock signal, for generating control and clock signals to selectively control the operation of said scannable synchronous/asynchronous CMOS latch circuit.

A LSI CMOS circuit chip comprising a plurality of scannable CMOS latch circuits, each scannable CMOS latch circuit comprising:

• a first latch circuit for latching a first output signal to a first level in response to a prescribed change in a data input signal applied to a first input terminal thereof, said first output signal being connected to a first output terminal, and for latching the first output signal to a second level in response to the application of a reset signal applied to a reset terminal thereof, said latching characterized by occurring without reference to any clocking signals;
• a second latch circuit connected to receive said data input signal from said first latch circuit and to latch a second output signal to a signal equivalent to the level of said data input signal immediately prior to the occurrence of a specified transition in a first clock signal applied to a clock terminal of said scannable synchronous/asynchronous CMOS latch circuit, and to maintain the latched level of sad second output signal for the entire duration of a cycle of said first clock signal said second output signal being connected to a second output terminal;
• scanning means for selectively shifting data held in said second latch circuit to a third output terminal;
• input means for selectively shifting data applied to a second input terminal of said scannable synchronous/asynchronous CMOS latch circuit directly into said second latch circuit;
• and
• select means, responsive to control signals including said first clock signal, for generating control clock signals to selectively control the operation of said scannable synchronous/asynchronous CMOS latch circuit;
• means for interconnecting the select means of each of said scannable CMOS latch circuits so that all operate in a same mode of operation in response to a first prescribed control signal applied to a control terminal of said chip.