Electron-beam lithographic apparatus
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorKiyomi Koyama
Life of this patent
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Abstract
A coordinate data memory is provided, in which a plurality of coordinate data representing partial patterns constituting a pattern to be drawn on a semiconductor wafer are stored. The coordinate data are supplied from the coordinate data memory to a plurality of coordinate data converters. The data converters convert coordinate data into address data by which pattern memories are specified respectively. Bit patterns are formed according to the address data in the pattern memories, respectively. The bit patterns of the pattern memories are synchronously read out bit by bit and synthesized in a logic gate circuit, and the resultant pattern is supplied to a blanking circuit bit by bit.
Claims7
An electron-beam lithographic apparatus comprising:
- means for generating address data corresponding to a plurality of partial patterns in parallel;
- pattern memory means specified in parallel by the address data from said address data generating means for forming bit patterns corresponding to said partial patterns in parallel;
- means for synchronously reading out in parallel said bit patterns from said memory means;
- means for synthesizing said bit patterns read out in parallel by said reading means to produce a resultant bit pattern in the form of bit data;
- and
- means for effecting blanking of an electron beam according to the bit data from said synthesizing means to thereby draw a pattern on an object;
- wherein said pattern memory means is constituted by a plurality of pair memories, and one bit pattern is formed in one memory in each of said pair memories while previously written bit pattern is being read out from the other memory in each of said pair memories.
An electron-beam lithographic apparatus, comprising:
- a main memory for storing a plurality of partial patterns;
- a data distributor connected to said memory for distributing said partial patterns from said memory;
- a plurality of parallel data converters for receiving said partial patterns from said data distributor;
- a plurality of pairs of parallel pattern memories, each of said pairs being connected to a corresponding one of said data converters;
- a plurality of pattern data readers, each of said readers being connected to a corresponding pair of pattern memories for receiving a partial pattern therefrom;
- a first pattern memory of each pair being connected to a data converter while a second pattern memory of each pair is connected to said data reader, said pattern memories alternating connections so that each pattern memory alternately receives and stores a partial pattern from said data converter and reads out said partial pattern to said data reader;
- a logic gate circuit for receiving a plurality of partial patterns from said plurality of data readers logically combining said partial patterns to form a complete pattern;
- a blanking circuit connected to said logic gate circuit for blanking an electron beam according to said complete pattern.
Dependencies are inferred from the claim text.