US 4,538,105 A · Overlay test wafer

Abstract

The present invention is directed to an improved test wafer for testing the overlay alignment of a second level pattern over a first level pattern for testing lithographic equipment used in making microcircuits, which includes four conductors with circuitry provided for each conductor measuring the conductance thereof, the conductors being constructed and arranged so that the conductance of the first conductor relative to the second conductor, and the conductance of the third conductor relative to the fourth conductor is indicative of the offset of said first level pattern with respect to said second level pattern. In another form of the invention four additional conductors are provided with circuitry provided for each conductor for measuring the conductance thereof, the additional conductors being constructed and arranged so that the relative conductance thereof is indicative of the offset of said first level pattern with respect to said second level pattern in a direction orthogonal with respect to the offset of the first group of four conductors.

Claims14

Dependent claims

A test wafer for testing the overlay alignment of a second level pattern over a first level pattern for testing lithographic equipment used in making microcircuits comprising:

a first conductor, means for measuring the conductance of said first conductor;
a second conductor, means for measuring the conductance of said second conductor;
a third conductor, means for measuring the conductance of said third conductor;
a fourth conductor, means for measuring the conductance of said fourth conductor;
said conductors being constructed and arranged so that the conductance of the first conductor with respect to the second conductor, and the conductance of the third conductor with respect to the fourth conductor is indicative of the offset of said first level pattern with respect to said second level of pattern.

2 more elements

A test wafer for testing the overlay alignment of a second level pattern over a first level pattern for testing lithographic equipment used in making microcircuits comprising:

a first conductor, means for measuring the conductance of said first conductor;
a second conductor, means for measuring the conductance of said second conductor;
a third conductor, means for measuring the conductance of said third conductor;
a fourth conductor, means for measuring the conductance of said fourth conductor;
a fifth conductor, means for measuring the conductance of said fifth conductor;
a sixth conductor, means for measuring the conductance of said sixth conductor;
a seventh conductor, means for measuring the conductance of said seventh conductor;
an eighth conductor, means for measuring the conductance of said eighth conductor,
said conductors being constructed and arranged so that the conductance of the first conductor with respect to the second conductor and the conductance of the seventh conductor with respect to the conductance of the eighth conductor is indicative of the offset of said first level pattern with respect to said second level pattern in a first direction;
and
said conductors being constructed and arranged so that the conductance of said third conductor with respect to said fourth conductor, and the conductance of said fifth conductor with respect to the conductance of the sixth conductor is indicative of the offset of said first level pattern with respect to said second level pattern in a orthogonal direction with respect to said first direction.

8 more elements

Dependencies are inferred from the claim text.

Overlay test wafer

Life of this patent

Overlay test wafer

Life of this patent

Abstract

Claims14