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AssigneeInternational Business Machines Corporation
InventorsAl M. Bracco, Arthur R. Edenfeld, Harish N. Kotecha
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The process sequence is disclosed which applies a polycrystalline silicon gate material, then applies a chemical vapor deposition oxide over all surfaces, forming an effective sidewall on each of the polycrystalline silicon gate structures. An ion implantation step is then carried out to implant source and drain regions whose proximate edges are not aligned with the edges of the polycrystalline silicon gate material itself, due to the masking effect of the sidewall portion of the chemical vapor deposition oxide layer. Thereafter, the chemical vapor deposition oxide sidewall material is selectively removed for those FET device locations where an active FET device is desired to be formed in the operation of personalizing the read only storage or PLA product. Those locations are then ion implanted for source and drain extensions which are then self-aligned with the respective edges of the respective polycrystalline silicon gate electrodes. The process enables a significantly reduced turnaround time for personalizing read only memory arrays which contain FET memory devices having a shorter channel length, higher breakdown voltage characteristic, an almost zero channel hot electron effect, and a lower gate-to-source/drain diffusion overlap capacitance than most other FET read only memory devices.
A process for forming a FET memory on a semiconductor substrate of a first conductivity type, having a gate insulator layer deposited on the surface thereof with a polycrystalline silicon gate electrode formed on the surface of said insulator layer, having a top surface and first and second opposed sidewall surfaces, comprising the steps of:
Dependencies are inferred from the claim text.