Process for manufacturing a semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMasahiko Denda, Shinichi Sato, Natsuro Tsubouchi, Shigeji Kinoshita, Yoshikazu Ohbayashi
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMasahiko Denda, Shinichi Sato, Natsuro Tsubouchi, Shigeji Kinoshita, Yoshikazu Ohbayashi
Estimating the term…
An n-channel MOS dynamic memory cell includes a semiconductor substrate having a p.sup.+ internal region and a p.sup.- surface region disposed on the surface of the internal region except for an n.sup.+ region serving as a bit line, a capacitor electrode disposed above the surface region, and a transfer gate disposed between the capacitor electrode and the n.sup.+ region above the surface region. The surface region except for the n.sup.+ region and a portion of the internal region disposed below the transfer gate are higher in resistivity than at least one of a portion of the internal region disposed below the capacitor electrode and another portion of the internal region disposed below the n.sup.+ region.
A process of manufacturing a semiconductor memory device comprising the steps of:
Dependencies are inferred from the claim text.