Static memory

A static memory comprising:

• a plurality of static memory cells which are arranged in the form of a matrix and each of which has a selection terminal and a pair of data terminals.
• a plurality of word lines each of which is connected in common with the selection terminals of the static memory cells,
• a plurality of paired data lines each of which is connected in common with respective paired data terminals of the static memory cells,
• a pair of common data lines,
• a switch circuit which couples the paired data line, to be selected among said plurality of paired data lines, to said pair of common data lines,
• a sense amplifier which has a pair of input terminals coupled to said pair of common data lines,
• a bias circuit connected between a power source line and said pair of common data lines which includes a MOSFET for applying bias voltages to said pair of common data lines, said bias voltages having values lowered with respect to a power source voltage fed to said power source line, and
• resistance means for coupling a current, of a value substantially equal to or somewhat greater than a leakage current developed by said MOSFET, between said MOSFET and a reference potential point of the circuitry.

A static memory comprising:

• a plurality of static memory cells which are arranged in the form of a matrix and each of which has a selection terminal and a pair of data terminals,
• a plurality of word lines each of which is connected in common to the selection terminals of the static memory cells,
• a plurality of paired data lines each of which is connected in common to the paired data terminals of the static memory cells,
• a pair of common data lines,
• a switch circuit which couples the paired data lines, to be selected among said plurality of paired data lines, to said pair of common data lines,
• a sense amplifier which has a pair of input terminals coupled to said pair of common data lines,
• a bias circuit connected between a power source line and said pair of common data lines which includes a MOSFET for applying bias voltages to said pair of common data lines, said bias voltages having values lowered with respect to a power source voltage fed to said power source line, and
• first and second resistance means connected between the respective common data lines and a reference potential point of the circuitry for coupling a current, of a value substantially equal to or somewhat greater than a leakage current developed by said MOSFET, between said MOSFET and said reference potential point.

A static memory comprising:

• a plurality of static memory cells which are arranged in the form of a matrix and each of which has a selection terminal and a pair of data terminals,
• a plurality of word lines each of which is connected in common to the selection terminals of the static memory cells,
• a plurality of pairs of data lines, each pair being connected in common to the data terminals of the static memory cells,
• a pair of common data lines,
• a switch circuit which couples one pair of data lines, to be selected amonth said plurality of pairs of data lines, to said pair of common data lines,
• a sense amplifier which has a pair of input terminals coupled to said pair of common data lines,
• a plurality of MOSFETs connected between a power source line and the respective data lines which apply bias voltages to the respective data lines, said bias voltages having values lowered with respect to a power source voltage fed to said power source line, and
• a plurality of resistance elements which are connected between said respective data lines and a reference potential point of the circuitry for coupling a current, of a value substantially equal to or somewhat greater than a leakage current developed by said plurality of MOSFETs, between said MOSFET and said reference potential point.