Avalanche fuse element in programmable memory
AssigneeTexas Instruments Incorporated
InventorDavid J. McElroy
Life of this patent
Estimating the term…
Abstract
A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used in a memory array of the PROM type. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuit.
Claims23
An electrically programmable semiconductor device comprising:
- a transistor having a source-to-drain path and a gate, and means for selectively activating the gate of the transistor for a sense operation, the source-to-drain path connected between a sense node and an access node,
- a thin dielectric separating the sense node from a common node,
- means for applying a high voltage to the sense node for selectively breaking down said dielectric due to an avalanche-mode current in said source-to-drain path to create an electrical short through said dielectric, the high voltage being less than the dielectric-breakdown voltage of said thin dielectric.
An electrically programmable semiconductor device comprising:
- a transistor having a source-to-drain path and a gate, and means for selectively activating the gate of the transistor for a sense operation, the source-to-drain path connected between a sense node and an access node,
- a thin dielectric separating the sense node from a common node,
- means for applying a high voltage to the sense node for selectively breaking down the dielectric in an avalanche mode to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric, wherein said common node is a conductor overlying a face of a semiconductor body, and the sense node is a region in said face partially underlying said conductor.
An avalanche-mode fuse element comprising field-effect type transistor means including source and drain regions in a face of a semiconductor body and a gate overlying the face between the source and drain regions, a thin-oxide break-down area between the gate and the face adjacent the drain region, and means for applying voltages to the source, drain and gate to break down said thin-oxide area by avalanche-mode current between said source-drain regions to create an electrical short between said gate and drain region, wherein the voltage across said thin-oxide break-down area is less than the dielectric breakdown voltage thereof.
A semiconductor read-only memory device comprising:
- an array of rows and columns of memory cells at a face of a semiconductor body, with row lines and column lines extending along said face,
- each of said cells including an access transistor and a storage element, the access transistor having a gate connected to a row line and having a source-drain path connecting a column line to a cell node,
- the storage element in each cell being connected between the cell node and a common node, and including a dielectric exhibiting a breakdown characteristic in response to programming voltage selectively applied to row and column lines.
A semiconductor read-only memory device comprising:
- an array of rows and columns of memory cells at a face of a semiconductor body, with row lines and column lines extending along said face,
- each of said cells including an access transistor and a storage element, the access transistor having a gate connected to a row line and having a source-drain path connecting a column line to a cell node,
- the storage element in each cell being connected between the cell node and a common node, and including a dielectric exhibiting a breakdown characteristic in response to programming voltage selectively applied to row and column lines,
- wherein the common node is a conductor extending along the face and separated from the face by said dielectric.
A semiconductor memory cell comprising:
- an access transistor connecting a sense node to an access line, and means for selectively activating the access transistor for read operation,
- a thin dielectric separating the sense node from a common node,
- means for applying a high voltage to the sense node for selectively breaking down the dielectric to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric.
A semiconductor memory cell comprising:
- an access transistor connecting a sense node to an access line, and means for selectively activating the access transistor for read operation,
- a thin dielectric separating the sense node from a common node,
- means for applying a high voltage to the sense node for selectively breaking down the dielectric to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric,
- wherein said common node is a conductor overlying a face of a semiconductor body, and the sense node is a region in said face partially underlying said conductor.
A method of making a semiconductor memory cell of the programmed read-only type comprising the steps of:
- applying a layer of conductive material on a face of a body of semiconductor material, and patterning the layer to form a transistor gate and a program-element gate overlying and separated from a transistor area and a program-element by thin insulator,
- forming heavily-doped regions in said face adjacent said transistor and program-element areas,
- applying an insulator coating on said face over said layer,
- forming openings in said insulator coating over some of said heavily-doped regions,
- applying conductive strips on said face over said coating and extending into said openings to form connections to the heavily-doped regions, and
- selectively applying a voltage to said conductive strips at a level less than the dielectric breakdown of said thin insulator to create electric short at the program element.
Dependencies are inferred from the claim text.