Self-calibrated clock and timing signal generator for MOS/VLSI circuitry

A self-calibrating clock and timing signal generator integratable into on-chip circuitry to provide arbitrary digital waveforms of preselected edge resolution comprising

• frequency generator means the frequency of which is calibrated according to a comparison with a reference frequency to develop a control signal to maintain its calibration,
• said frequency generator means including a first voltage control oscillator having a plurality of first delay stages coupled to one another by first signal pass means, the output of which is said frequency,
• said control signal coupled to each of said first signal pass means,
• tapped delay line means having means to receive an input signal and comprising a second voltage control oscillator and having a plurality of second delay stages coupled to one another by second signal pass means with a selectable tap output between at least several of said second delay stages,
• said control signal coupled to each of said second signal pass means,
• said first and second delay stages and said first and second signal pass means being of identical structure,
• circuit means coupled to selected of said output taps to produce at least one such digital waveform of preselected edge resolution.

A method of providing arbitrary digital waveforms of preselected edge resolution based upon a known reference frequency comprising the steps of:

• providing a ring oscillator comprising a series of delay stages coupled to one another by signal passing means to produce an output frequency,
• comparing the output frequency with said reference frequency to produce a voltage control signal representative of the frequency difference between said reference frequency and said output frequency,
• supplying said control signal to the signal pass means of said oscillator to control the frequency of said output frequency to be the same or multiple of said reference frequency,
• providing a delay line having a plurality of output taps capable of providing a preselectable delay to an input signal supplied thereto and comprising a series of delay stages coupled to one another by signal pass means identical in structure to the delay stages and signal pass means of said oscillator,
• supplying the control signal to the signal pass means of said delay line so that the unit delay per stage is continually the same based upon said reference frequency, and
• selecting an output from at least one pair of said taps to produce a waveform of predetermined edge resolution and duty cycle based primarily upon the number of stages in said delay line and the selection of said reference frequency.