Data line interface for a time-division multiplexing (TDM) bus

A data line interface, for transferring data from a source to a specified destination channel in a data line interface, comprising:

• bus for receiving and transferring parallel data characters, and address and command signals, each of said data characters being preceded by a start bit and being ended by a stop bit,
• command decoder means coupled to said bus means for receiving address and command signals from said bus means, and generating command signals in response thereto,
• input data means coupled to said bus means for receiving said data characters from said bus means,
• first memory means coupled to said input data means for receiving and storing said parallel data character from said input data means in response to a command from said control means,
• second memory means coupled to said first memory means for receiving and storing said parallel data character from said memory means,
• memory manager means coupled to said first and second memory means for regulating the flow of said data character from said first memory means to said second memory means in response to a command from said control means,
• bit transmitter means for converting and retiming the parallel data character received from said second memory means into a serial format,
• bit sampling means for sampling said stop bit, said bit sampling means reading said stop bit during only a portion of said stop bit and thereafter causing said memory manager means to move the next data character from said second memory means to said bit transmitter for conversion of said next data character into serial format thereby allowing said bit transmitter to read the next data character after only a portion of said stop bit;
• first error detecting means for monitoring the first and second memory means to indicate when both of said memories have a data character contained therein, and also indicating when the first memory means can receive a new data character;
• and
• a second error detecting means coupled to said first and second memory means for indicating an overrun error when new data is received from said bus means when both of said memories have data characters stored therein, and for providing a means for indicating that the data has a parity error;
• and
• output buffer means coupled to said first and second error detecting means for driving said error information to said bus means;
• whereby the parallel data character from said bus means is converted into serial format and said stop bit is shortened in response to a command from said memory manager means wherein new parallel data can be immediately received from said second memory means such that an overflow of data does not occur.

A system for converting parallel data from a source to serial format for transmission to a specific destination channel, comprising:

• bus means for receiving and transferring parallel data, address and command signals, each of said data signals forming a character being preceded by a start bit and being ended by a stop bit;
• command control decoder means for receiving the command address and signals from said bus means comprising a state clock means for controlling the flow of said data from said bus means,
• first memory means coupled to said command control decoder means, for receiving and storing parallel data from said bus means in response to a command from said control means,
• second memory means coupled to said first memory means for receiving and storing the data from said first memory means,
• memory manager means coupled to said first and second memory means for regulating the flow of data from said first memory means to said second memory means in response to a signal from said control means, and
• bit transmitter means coupled to receive parallel data from said second memory means comprising first means for generating a start bit in response to a command received from said memory manager means, and second means for converting said parallel data into serial data, said first means generating a stop bit at the end of said serial data,
• bit sampling means for sampling said stop bit, said bit sampling means reading said stop bit during only a portion of said stop bit and thereafter causing said memory manager means to move the next character from said second memory means to said bit transmitter for conversion of said next character into serial format thereby allowing said bit transmitter to end the next character after only a portion of said stop bit,
• whereby said stop bit is shortened in response to a command from said memory manager means wherein new parallel data can be immediately received from said second memory means such that an overflow of data does not occur.