Lock detecting circuit for phase-locked loop frequency synthesizer

A phase-locked loop circuit comprising:

• a reference oscillator providing a first output signal;
• a reference frequency divider, operatively connected to said reference oscillator, for dividing the frequency of the first output signal of said reference oscillator by a predetermined value and producing a second output signal having a frequency corresponding to the divided frequency of the first output signal;
• a voltage controlled oscillator providing a third output signal;
• a programmable frequency divider, operatively connected to said voltage controlled oscillator, for dividing the frequency of the third output signal by a controlled variable value to produce a fourth output signal;
• a phase comparator, operatively connected to said programmable frequency divider and said reference frequency divider, for receiving and monitoring the difference in phase between the fourth and second output signals and providing first and second phase output signals, respectively;
• a low pass filter, operatively connected between said phase comparator and said voltage controlled oscillator, for controlling said voltage controlled oscillator in dependence upon the first and second phase output signals of said phase comparator;
• lock detector means, operatively connected to said phase comparator, for generating a first lock detecting signal which is pulsed when a difference in phase is detected between said fourth and second output signals;
• and
• digital signal maintaining circuit means, operatively connected to said lock detector means and said reference frequency divider, for converting the first lock detecting signal into a second lock detecting signal having a direct current level, maintaining the second lock detecting signal for a predetermined time after the first lock detecting signal is extinguished and providing an output signal, said digital signal maintaining circuit means comprising:
• converter circuit means, operatively connected to said reference frequency divider and said lock detector means, for converting the first lock detecting signal into the second lock detecting signal in dependence upon the second output signal and outputting the second lock detecting signal;
• and
• maintaining circuit means, operatively connected to said converter circuit means, for maintaining the potential of the second lock detecting signal for the predetermined time after the first lock detecting signal is extinguished and providing the output signal.