Sense amplification scheme for random access memory
AssigneeAdvanced Micro Devices, Inc.
InventorsPatrick T. Chuang, Paul D. Keswick
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorsPatrick T. Chuang, Paul D. Keswick
Estimating the term…
In source-clocked type of cross-coupled latch sense amplifier of a dynamic random access memory device, there is provided a sense clock that employs multiple extended dummy memory cells to provide reference timing which tracks time constants of word line, cell transfer gate, cell capacitor, and bit line, and the sense clock is further compensated over large variations of fabrication process parameters and operating conditions. The trigger and slave clock circuit are chained in series to control the timing sequence of a plurality of clocked output signals. The clocked output signals are selectively amplified and summed in parallel to generate current with an intended dynamic characteristic. The current so generated is applied to the common source electrodes of the cross-coupled latch.
For use in a capacitive storage integrated circuit memory device having at least one sense amplifier of a type employing a latch including cross-coupled field effect transistors with common source electrodes, said sense amplifier for sensing and comparing charge on a bit line coupled to each drain electrode of each one of said transistors of said latch, each said bit line being selectively coupled to a storage cell through a transistor switch transfer gate in response to signals applied to a word line, an apparatus for controlling sense rate of said bit lines comprising:
Dependencies are inferred from the claim text.