CMOS Reset circuit
AssigneeNational Semiconductor Corporation
InventorsGerald B. Buurma, John M. Jorgensen
Life of this patent
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Abstract
A CMOS integrated circuit power-on reset circuit has two cascaded threshold detectors for independently sensing the supply voltage attaining an amplitude sufficient to operate N and P-channel devices respectively and for providing a reset signal in response to the supply voltage meeting both conditions.
Claims11
A CMOS integrated power-on reset circuit for providing an output signal in response to the application of a voltage across a supply terminal and a reference terminal;
- the circuit comprising:
- a first circuit comprising a first capacitor having a first terminal and a second terminal, a first N-channel transistor having a drain coupled to the second terminal of the first capacitor, a source coupled to the reference terminal, and a gate, and first circuit means including a forward-biased diode coupled between the supply and reference terminals in series circuit with the gate and source of the first N-channel transistor;
- a second circuit comprising a second capacitor having a first terminal coupled to the reference terminal and a second terminal, a first P-channel transistor having a drain coupled to the second terminal of the second capacitor, a source coupled to the supply terminal, and a gate, and second circuit means including a forward-biased diode coupled between the supply and reference terminals in series circuit with the source of the first P-channel transistor;
- inverter means comprising a second P-channel transistor coupled in series circuit with a second N-channel transistor between the supply and reference terminals, the gates of the second transistors coupled, for providing the output signal in response to the voltage applied to the gates of the second transistors;
- wherein the second terminal of the capacitor of one of the first and second circuits is coupled to the gate of the transistor of the other of the first and second circuits and the second terminal of the capacitor of the other circuit is coupled to the gates of the second transistors.
A CMOS integrated power-on reset circuit for providing an output signal in response to the application of a voltage across a supply terminal and a reference terminal, the circuit comprising:
- a first circuit comprising a first first capacitor having a first terminal coupled to the supply terminal and a second terminal, a first N-channel transistor having a drain couple to the second terminal of the first capacitor, a source coupled to the reference terminal, and a
- a second circuit comprising a second capacitor having a first terminal coupled to the reference terminal and second terminal, a first P-channel transistor having a drain coupled to the second terminal of the second capacitor, a source coupled to the supply terminal, and a gate;
- inverter means comprising a second P-channel transistor coupled in series with a second N-channel transistor between the supply and reference terminals, the gates of the second transistors coupled, for providing the output signal in response to the voltage applied to the gates of the second transistors;
- wherein the second terminal of the capacitor of one of the first and second circuits is coupled to the gate of the transistor of the other of the first and second circuits and the second terminal of the capacitor of the other circuit is coupled to the gates of the second transistors;
- further comprising a forward biased diode having an anode coupled to the supply terminal and a cathode coupled to the source of the first P-channel transistor, the gate of the first P-channel transistor coupled to the reference terminal, the second terminal of the second capacitor coupled to the gate of the first N-channel transistor, and the second terminal of the first capacitor coupled to the gates of the second transistors.
A CMOS integrated power on reset circuit for providing an output signal in response to the application of a voltage across a supply terminal and a reference terminal, the circuit comprising:
- a first voltage reference circuit coupled between said supply and said reference terminal, including a first MOSFET and a first diode connected thereto for establishing a first threshold voltage;
- a second voltage reference circuit coupled between said supply and said reference terminal and a terminal of said first voltage reference circuit and including a second MOSFET of complementary type of said first MOSFET and a second diode connected thereto for establishing a second threshold voltage;
- a CMOS inverter circuit connected to the output of said second voltage reference circuit and providing the output of said reset circuit in response to said supply terminal voltage exceeding the higher of said first or second threshold voltage.
Dependencies are inferred from the claim text.