Integrated digital semiconductor circuit

Integrated digital semiconductor circuit, comprising n terminals, a common constant current source for supplying said terminals, said current source being in the form of a transistor having a current supplying output, each of said terminals being operable in an identical logic level "1" in one operating state and each of said terminals being operable in an identical logic level "0" in another operating state, the digital semiconductor circuit being operable in one operating state in which all of said terminals are at the logic level "0" and in remaining operating states in which a given partial number of said terminals are at the logic level "1" and the others of said terminals are at the logic level "0", n equal resistors each being connected between said current supplying output and a respective one of said terminals, said resistors forming an exclusive connection between said constant current source and said terminals, said resistors having resistance values R being adjustable according to the formula:

• ##EQU3## where U is the voltage excursion between the logic level "0" and the logic level "1", k is the ratio between the current flowing through one of said terminals at the logic level "1" and the current flowing through the one terminal at the logic level "0", and I is the value of the total current flowing through all of said terminals in said operating states.