Semiconductor RAM device
AssigneeFujitsu Limited
InventorSetsuo Kurafuji
Life of this patent
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Abstract
A static type semiconductor RAM device comprising a latch circuit at every column which detects, amplifies and temporarily memorizes a read-out signal from each of the memory cells in the corresponding column and which has a large drive capacity. In the static type RAM device according to the present invention, each of the memory cells is used as an element which only holds information, and data bus lines are driven by the latch circuits having a large drive capacity, so that the slow down of the read-out speed and the decrease of reliability of read-out data of the static type RAM device having a large memory capacity is prevented.
Claims9
A semiconductor RAM device having a matrix of rows corresponding to word lines and columns corresponding to bit lines, and static type memory cells, respective of the static type memory cells operatively connected at corresponding of the cross points of said matrix,
- a row decoder having outputs respectively, operatively connected to corresponding ones of said rows;
- a column decoder having outputs respectively, operatively connected to corresponding ones of said columns;
- each of said static type memory cells being selected by the respective output from the row decoder and the respective output from the column decoder and generating a data signal in response to being selected, said semiconductor RAM device comprising:
- amplifier circuits, having activated and non-activated states, respective of said amplifier circuits operatively connected to corresponding of said bit lines, for amplifying the data signal from a selected one of said static type memory cells associated with said corresponding bit lines, and
- gate circuits having activated and non-activated states, respective of said gate circuits operatively connected between said corresponding bit lines and said respective amplifier circuits, said gate circuits being activated for a first specified period after a respective memory cell is selected by said output from said row decoder and said output from said column decoder and passing the data signal from said respective memory cell to said corresponding amplifier circuit,
- said amplifier circuit being selectively activated for a second specified period after said first specified period.
Dependencies are inferred from the claim text.