Memory mapping unit

A memory mapping unit used to map a 2.sup.K size memory board to any 2.sup.N address boundary, for a 2.sup.M memory space having a M bit address buss connected in parallel to each memory board, the 2.sup.K memory board can range in size from N.ltoreq.K.ltoreq.M, each memory board mapping unit is associated with a particular memory board and produces a board enable command when the address carried by the address buss identifies the location on the memory board, comprising:

• a base address register containing at least (M-N) bits for storing the 2's complement of the base address of the memory board;
• an adding means connected to said base address register and the address buss for adding the value of the base address register with the upper (M-N) bits of the memory address;
• a board size mask register containing at least (M-N) bits for masking out bits which are not useful for a particular board size such that for a 2.sup.K board, the first (K-N) least significant bits in said board size register should be "zero" and the upper (M-K) bits should be "one";
• a first logical means connected to said adding means and said board size mask register for performng an AND operation on each bit in said adding means with it's corresponding bit position in said board size mask register;
• and
• a second logical means connected to said first logical means for performing a NOR operation on the outputs from said first logical means and producing said board enable command when all of said outputs are in a predetermined logic condition, which turns on the memory board when the memory address identifier is located on the board.