US 4,400,793 AGranted

Method and arrangement for fast access to CCD-stores

AssigneeInternational Business Machines Corporation

InventorClaus Schuenemann

Life of this patent

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Abstract

To reduce the mean access time to storage blocks in CCD storage, a block which is most likely to be accessed next is detected after each access. While the accessed block is being processed, a selected block is moved at the high cyclic speed of the CCD storage to a shift position, and the CCD storage is then switched to the low speed. The distance of the shift position from a read/write position is such that it can be covered by the selected block at low speed within the mean time between two accesses to the CCD storage. At the time of the next access, the selected block is very likely to be close to the read/write position. In systems with virtual addressing, the block with the next virtual address would be the selected block. In other layouts, the access sequences to the CCD blocks are stored and are subsequently used to select the block which is most likely to be accessed next.

Claims3

Dependent claims

The method of transfer of units of data between a random access storage and a slower cyclic storage which operates at a fast cyclic speed when it is accessed for transfer of data and a slow cyclic speed when it is not so accessed and which stores each of a plurality of units of data in a separate one of a plurality of storage locations that move passed the accessing point in series comprising,

(a) arranging data units in the cyclic store so that units of data that follow each other in the expected accessing sequence are not in adjacent storage locations but are separated from one another by at least one other storage location containing another unit of data so as to place the unit of data expected to be accessed next where it can be reached at the slower cyclic speed in the mean time between two accesses,
(b) recording an actual accessing sequence of the units of data,
(c) operating the cyclic memory at the fast cyclic speed between accesses until the unit of data occurring next the recorded actual accessing sequence is moved to a position where it can be reached at the slow cyclic speed in the mean time between two accesses,
(d) operating the cyclic memory at the slow cyclic speed after step c and until the next access and
(e) operating the memory at the fast cyclic speed while the unit of data requested by said next access approaches the accessing point.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/350,456Filed 19 Feb 1982 · continuation
Priority: DE 285350112 Dec 1978
Granted: 23 Aug 1983
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 12/0802
In hierarchically structured memory systems, e.g. virtual memory systems: addressing of a memory level in which the access to the desired data or…
G11C 19/287
Using semiconductor elements: organisation of a multiplicity of shift registers
G06F
Computing and data processing
G11C
Static stores

Family

Serial86,215Parent of this continuation · filed 18 Oct 1979
US 4,400,793 AThis patent

From the US filing history. Foreign family members aren’t listed.

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