Large-volume, high-speed data processor

A data processing subsystem (12) associated with a host computer (10) said host computer including means for generating a queue of transaction command packets, comprising:

• a supervisor (14) for receiving from said host computer at least one transaction command packet, said transaction command packet consisting of a plurality of supervisor command packets, said supervisor further including means for transforming selected supervisor command packets into device command packets;
• a direct device access bus (18, 20);
• a command control bus (52)
• a plurality of peripheral devices (22, 24, 26, 28) having equal priority, each being interfaced to said direct device access bus and to said command control bus by its own dedicated programmable general purpose device adapter (32/42, 34/44, 36/46, 38/48);
• register means (95) in each said programmable general purpose device adapter for receiving from said supervisor over said command control bus, a selected device command packet including a unique transaction code for identifying certain ones of said plurality of peripheral devices as being members of one of several different sets of devices, a separate transaction code being assigned to each specific set and to all of the members thereof;
• a bus controller (16) interconnected between said supervisor and said direct device access bus;
• means in said bus controller, for establishing a plurality of time slots and a register means (41) for associating, in cooperation with said supervisor, selected time slots with selected transaction codes;
• and
• means (39) for enabling substantially concurrent direct data transfers between members of the respective device sets over the direct device access bus during specified time slots, a different time slot being assigned to each different set.