US 4,400,775 AGranted

Shared system for shared information at main memory level in computer complex

AssigneeTokyo Shibaura Denki Kabushiki Kaisha

InventorsMasaharu Nozaki, Hiroshi Nakamura, Yusaku Miki

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Abstract

A computer arrangement for facilitating the sharing of information among computers at a memory level. Each computer includes means for accessing the main memory of another computer of the complex at machine word level, means for transmitting an interruption instruction from itself to the arithmetic control unit of the other computer, means for detecting a problem in the arithmetic control unit of itself, and means for altering one section of the logic address viewed from itself to some of a plurality of physical address spaces such as to make the same the logic address of a shared information storage region of the computer complex viewed from the program of each of the member computers. Shared information required for each computer is stored in its own main memory. When a problem occurs in the computer having the aforesaid shared information storage region it becomes evident in the computer's arithmetic control unit. As a result, an interruption instruction is sent to each of the other computers. The computers receiving the interruption permit the shared information stored in their own main memories to be transferred through the access enabling means to the main memories of the other computers to be written therein thereby restoring the shared information storage region, and permitting continual data processing.

A system for accessing shared information at a main memory level in a computer complex comprising a plurality of computers operatively coupled to one another for data processing, each computer having the capability of being either a host computer or a slave computer, at least one of the computers having a shared information storage region in its main memory means, each said computer comprising:

(a) main memory means for storing at least local data to be processed within said computer;
(b) means, coupled to said main memory means, for controlling the reading of data therefrom and the writing of data therein;
(c) arithmetic control means, coupled to said main memory control means, for controlling data processing operations involving said local data;
(d) computer system linkage memory means, coupled to said main memory controlling means, for enabling access to said main memory means of all other computers through their corresponding computer system linkage interrupt means at a machine word level, thereby permitting the writing of shared information stored in the main memory means of the one of said computers into said main memory means of all other computers;
(e) alarm means, coupled to said arithmetic control means, for detecting a problem in said arithmetic control means;
(f) computer system linkage interrupt means, coupled to said arithmetic control means and alarm means, for transmitting an interrupt instruction to said arithmetic control means of all the other computers through their corresponding computer system linkage interrupt means in accordance with a command from said computer system linkage memory means or said alarm means;
(g) high speed input/output bus means for connecting said computer system linkage memory and said computer system linkage interrupt means;
and
(h) means operatively connected to said arithmetic control means for altering one section of a logic address space viewed from each said computer to any one of a plurality of sections of a physical address space so that the logic addresses of the shared information storage region which are respectively viewed from the programs of said computers are identical.

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Abstract

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