Cache addressing arrangement in a computer system

A computer system comprising

• a processor for generating and transmitting a read control signal and virtual address signals including word address signals;
• address translation means responsive to certain of said virtual address signals for generating present cache address signals and other address signals;
• cache memory means comprising tag memory means for storing tag data words, and data memory means for storing information data words;
• memory access control means comprising address storage means for storing previous cache address signals and cache control means responsive to said read control signal to transmit a first cache control signal and the stored previous cache address signals to said cache memory;
• said memory access control means further comprising comparator means for comparing said stored address signals and said present cache address signals to generate a first comparison signal if said stored address signals equal said present cache address signals and to generate a second compare signal if said stored address signals are not equal to said present cache address signals;
• said tag memory and said data memory being responsive to said first cache control signal, said stored address signals, and said word address signals to read a tag data word and an information data word, respectively;
• cache address comparison means responsive to said other address signals and said tag data word to generate and to transmit to said cache control means a third compare signal if said other address signals equal said tag data word and to generate a fourth compare signal if said other address signals do not equal said tag data word;
• and
• said cache control means is responsive to concurrent generation of said first and said third compare signals to generate and to transmit said completion signal to said processor.