Method and apparatus for direct memory access in a data processing system

In a data processing system comprising a data transfer means which is capable of direct memory access to data associated with a central processing unit, said data transfer means having data ports capable of data transfer, independent of said cantral processing unit, a central processing unit with a data port, an address port and an interrupt port, said central processing unit being responsive to specific external digital signals, such as interrupt signals and instruction signals, for issuing digital address signals to an addressable memory space, memory means for storing data associated with said central processing unit and arranged in memory units, each said memory unit having memory locations with addresses within said memory space, an address port and a data input/output port, the improvement comprising:

• an address decoder having an address input port and a control output port, said decoder being coupled to a third bus means and operative to generate specific digital control signals in response to address information directed by said central processing unit to addresses, designated herein vacant addresses, in said memory space which are addresses other than of said memory locations of said memory means, said address information being operative to permit transfer of instruction control from said central processing unit;
• means having an address input port and a data output port for generating digital data representative of instructions for said central processing unit;
• first bus means coupling together said data port of said instructions generating means and said data port of said central processing unit;
• second bus means coupling together each said data port of said memory means and said data port of said data transfer means;
• third bus means coupling together said address port of said instructions generating means, with each said address port of said memory means and said central processing unit;
• and
• gate means coupled to said third bus means and to specific portions of said memory means for allocating address information directed at selected portions of said memory space to other portions of said memory space within said memory means, said address decoder further being coupled through control output ports to said data transfer means and operative through said control output ports to enable data transfer between said memory means via said second bus means through said data port of said data transfer means in response to receipt of special addresses from said central processing unit designated for use with instructions external of said central processing unit.