US 4,400,771 AGranted

Multi-processor system with programmable memory-access priority control

AssigneeTokyo Shibaura Electric Co., Ltd.

InventorsSeigo Suzuki, Seiji Eguchi

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Abstract

A multi-processor system includes a plurality of processors, a common shared memory, and programmable memory access priority control circuit. The programmable memory access priority control circuits includes a programmable register circuit and a priority control circuit. The programmable register circuit stores priority information designating a memory access grade priority for each of the processors, wherein the priority information is changeable either manually, by external circuit or by at least one of the processors and remains fixed irrespective of access of the memory by any of the processors until being changed. The register circuit outputs priority information signals which indicate the memory access grade priority of each of the processors. The priority control circuit receives the priority information signals from the register means, receives a memory request signal from the processors requesting memory access (i.e. use) of the common shared memory, and outputs an acknowledge signal enabling the processor having the highest memory access grade priority to use the common shared memory in accordance with the priority information.

Claims9

Dependent claims

A multi-processor system comprising:

a plurality of processors;
a common shared memory for use by said processors, said processors each adapted to generate a respective memory request signal to request access to said common shared memory;
a bus connected to said processors and said memory for transferring data from said processors to said memory or from said memory to said processors;
register means for storing priority information designating a memory access grade priority for each of said processors, said priority information changeable in a predetermined manner and remaining fixed irrespective of access of said memory by any of said processors until being changed in said predetermined manner, said register means outputting priority information signals which indicate the memory access grade priority of each of said processors;
and
priority control means for receiving said priority information signals from said register means, for receiving said memory request signals from said processors when said processors request access of said memory, and for outputting an acknowledge signal enabling memory access to that processor requesting use of the memory and having among the processors requesting memory access the highest memory access grade priority stored in said register means;
whereby the priority of memory access of said processors is changed by changing the contents of said register means.

4 more elements

A multi-processor system comprising:

a plurality of processors;
a common shared memory for use by said processors, said processors each adapted to generate a respective memory request signal to request access to said common shared memory;
a bus connected to said processors and said memory for transferring data from said processors to said memory or from said memory to said processors;
first register means for storing first priority information designating a first memory access grade priority for each of said processors, said first priority information changeable in a predetermined manner and remaining fixed irrespective of access of said memory by any of said processors until being changed in said predetermined manners, said first register means outputting first priority information signals which indicate the first memory access grade priority of each of said processors;
second register means for storing inhibit information which can be changed, and for outputting inhibit information signals which inhibit selected ones of said processors from using the common shared memory;
gate means for receiving said first priority information signals from said first register means, for receiving said inhibit information signals from said second register means, and for outputting second priority information signals which indicate a second memory access grade priority of each of said processors with the selected ones of said processors inhibited by said second register means;
and
a priority control means for receiving said second priority information signals from said gate means, for receiving said memory request signals from said processors when said processors request memory access of said memory, and for outputting an acknowledge signal enabling memory access to that processor requesting use of the memory and having among the processors requesting memory access the highest second memory access grade priority in accordance with the condition of said second priority information signals outputted by said gate means.

5 more elements

Dependencies are inferred from the claim text.