Overvoltage protection circuit
AssigneeGeneral Electric Company
InventorGeorges R. E. Lezan
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AssigneeGeneral Electric Company
InventorGeorges R. E. Lezan
Estimating the term…
An overvoltage protection circuit for a circuit array including one or more semiconductor devices such as thyristors derives its energization solely from the voltage across the array. A unidirectional current is developed to respond to that voltage and this current is utilized to develop an electrical charge of not more than a predetermined magnitude. The unidirectional current is also utilized to develop a signal which is proportional to the voltage across the array. When this signal reaches a predetermined level, indicative of an overvoltage condition of the array, a switching current is rendered operative to cause the stored charge to be applied to the gating electrodes of the array semiconductor devices to thereby render each such device conductive.
An overvoltage protection circuit for a circuit array comprised of one or more semiconductor devices each having anode, cathode and gate electrodes, said array being connected intermediate a source of electrical power and a load and serving, upon the application of gating pulses to the gate electrodes, to deliver electrical power from the source to the load, said overvoltage protection circuit comprising:
An overvoltage protection circuit for a circuit array comprised of one or more semiconductor devices each having anode, cathode and gate electrodes, said array being connected intermediate a source of electrical power and a load and serving, upon the application of gating pulses to the gate electrodes, to deliver electrical power from the source to the load, said overvoltage protection circuit comprising:
An overvoltage protection circuit for a plurality of series connected semiconductor devices comprising:
An overvoltage protection circuit for a plurality of series connected semiconductor devices, each having a gate electrode, adapted to be rendered conductive by single firing pulse operative to apply simultaneous gating pulses to the individual gate electrodes of the semiconductor devices comprising:
Dependencies are inferred from the claim text.